Power factor correction (PFC) circuit

Details Power factor correction (PFC) circuit Power factor correction (PFC) circuit

1999-05-24

2001-07-10

Patel, Rajnikant B. (Department: 2838)

Electric power conversion systems

Current conversion

With condition responsive means to control the output...

C363S127000, C323S222000, C323S284000

Reexamination Certificate

active

06259613

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims priority from Korean Priority Document No. 98-18470, filed on May 22, 1998 with the Korean Industrial Property Office, which document is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a power factor correction (PFC) circuit. More specifically, the present invention relates to a PFC circuit for controlling a phase of an input current to be identical with a phase of an input voltage by adjusting a duty ratio of a switch using the input current detected on the ground potential.
2. Description of the Related Art
FIG. 1
shows a conventional PFC circuit. A filter
1
and a bridge diode
2
rectify AC power from an AC
14
source to supply an input voltage Vs smoothened by a capacitor C
1
. An input current i
L
is supplied to a primary side of an inductor L, which is switched according to the ON and OFF states of the switch
3
, which is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Accordingly, an output voltage Vo is supplied to a load. A diode D
1
and a capacitor C
2
rectify the output voltage Vo so as to supply the rectified voltage Vout to an adjustable load Ro.
The circuit also includes a controller
40
. A reference voltage Vref is supplied to an error amplifier
4
through a noninverting input terminal. A voltage, produced by dividing Vout with two resistors R
1
and R
2
, is supplied to the error amplifier
4
through an inverting input terminal. The error amplifier
4
amplifies a difference voltage by a predetermined ratio, and outputs the amplified voltage Veo to an subtractor
5
. The subtractor
5
subtracts the reference voltage Vref from the voltage Veo, and outputs a voltage V
2
.
A resistive divider made by resistors R
3
and R
4
produces a voltage V
1
. A multiplier
6
multiplies the voltage V
2
and a voltage V
1
, and outputs a multiplied voltage Vmo.
A comparator
7
compares the voltage Vmo with a voltage of a resistor Rs which is coupled between the source of the switching MOSFET
3
and the ground. A latch circuit
8
logically latches signals provided from the comparator
7
and a current detector
9
, and outputs the latched signal to a logical NOR gate
10
.
The current detector
9
detects a current flowing through the inductor L in order to control the switch
3
. The logical NOR gate
10
executes a logical NOR operation on the signals provided from the latch circuit
8
and the current detector
9
, so as to control the switch
3
. Therefore, when the input voltage Vs is increased (or reduced) and the voltage V
1
which detects the amount of fluctuation that the input voltage Vs is increased (or reduced), the multiplied voltage Vmo is increased (or reduced), and the turn on duty ratio of the switching MOSFET
3
is altered, thereby, the output voltage Vo is increased (or reduced).
However, since the resistor Rs to detect the input current flowing through the inductor is coupled between the source of the switching MOSFET and the ground, when the switching MOSFET is turned on, it exhibits poor characteristics, such as switching noise. Additionally, all three of the input current, input voltage, and the output voltage need to be detected in order to compensate for the power factor. This complicates the circuit and increases its cost.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a power factor correction circuit for detecting information on input current on the ground potential and adjusting the turn on duty ratio by using the detected input current, thereby controlling the phase and amplitude of the input current to be identical with those of the input voltage.
In one aspect of the present invention, one end of the detection resistor Rs is coupled to a point at which the source of the switching MOSFET is grounded, and the other end of the resistor Rs is coupled to a voltage amplifier. The input current is detected by the voltage drop across both the ends of the detection resistor Rs, and the voltage is amplified by the voltage amplifier and is output to a multiplier. Since Rs is partially grounded there is less noise.
The circuit further provides a multiplier that multiplies together the voltage supplied from the voltage amplifier and a secondary side error voltage that is representative of the output voltage. The multiplier outputs a multiplied voltage. The multiplied voltage is compared to a reverse sawtooth waveform for controlling the duty ratio of the switching MOSFET.
The resulting circuit is simpler because it only detects the input current and input voltage, i.e., only two quantities. These and other advantages will be better appreciated in view of the attached drawings and Detailed Description of the invention.


REFERENCES:
patent: 5644214 (1997-07-01), Lee
patent: 5764039 (1998-06-01), Choi et al.
patent: 5804950 (1998-09-01), Hwang et al.

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