Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1989-03-24
1990-02-13
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Data refresh
365193, 36518901, 365233, G11C 700, G11C 800
Patent
active
049012827
ABSTRACT:
In a static column dynamic random access memory device in which memory operations including refresh operation are initiated responsive to a row address strobe signal, and the refresh operation for amplification and rewriting of information of the selected memory cell is not interrupted until its completion once it is started by the application of the row address strobe signal even if the row address strobe signal is thereafter removed;
a timing circuit provides clocks for controlling the row circuits and the column circuit to cause termination of the memory operations if the row address strobe signal has been removed before the end of the refresh operation, and to cause continuation of the read/write memory operations if the row address strobe signal is still applied at the end of the refresh operation.
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Baba et al., "A 64K DRAM with 35 ns Static Column Operation," 18, Journal of Solid-State Circuits, 447, (1983).
B. Normann, "Static Column RAM Almost Doubles Data Rates," Electronic Design, Feb. 23, 1984, at 259.
Baba et al., "A 35 ns 64K Static Column DRAM", 1983 IEEE Int'l Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 23, 1983, at 64.
Hecker Stuart N.
Koval Melissa J.
Mitsubishi Denki & Kabushiki Kaisha
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