Power efficient method for controlling an oscillator in a...

Details Power efficient method for controlling an oscillator in a... Power efficient method for controlling an oscillator in a...

2011-08-30

2011-08-30

Du, Thuan N (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S322000, C710S061000

Reexamination Certificate

active

08010818

ABSTRACT:
In a method and apparatus for saving power in a device coupled to a bus, the device is placed to operate in a power saving mode by powering off a selective portion of the device including a device clock. If data communication over the bus is addressed to the device then the selective portion of the device, including the device clock, is triggered to return to a power on state from the power off state. The data communication is stored in shadow registers using a bus clock while the device clock is transitioning to the power on state. The data communication stored in the shadow registers is transferred to a register map under the control of the device clock operating in the power on state. Upon completion of the transfer of the data communication to the register map, the device is returned to operate in the power saving mode.

REFERENCES:
patent: 6047378 (2000-04-01), Garrett et al.
patent: 6301673 (2001-10-01), Foster et al.
patent: 7243250 (2007-07-01), Ueda
patent: 7694025 (2010-04-01), Norrie

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