Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2002-09-09
2004-06-01
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C257S341000, C257S495000, C257S653000, C257S401000, C257S133000, C257S155000, C257S355000
Reexamination Certificate
active
06743703
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to power semiconductor diodes and rectifiers, and more particularly the invention relates to a power diode having a reduced on resistance and higher reverse breakdown voltage.
A two-terminal power diode or rectifier must have a low turn-on voltage, fast turn-off voltage, and nonconductance when the diode is reverse biased. In addition, the on-resistance must be low and the reverse bias breakdown voltage must be high. However, the necessary doping for low on-resistance can adversely affect reverse breakdown voltage.
Three-terminal vertical MOSFET devices are known which have an alternating P and N doped channel region for connecting a source region on one surface to a drain region on an opposing surface. The alternating P and N regions provide a balanced space charge and reduced electric field below the critical field strength at which avalanche breakdown would occur. Yet the on resistance is not adversely affected. See for example, U.S. Pat. Nos. 5,216,275; 5,438,215; 6,274,904; 6,274,904, 6,037,631; and 6,066,878, for example.
The present invention is directed to improving the characteristic of two-terminal power diodes, such as Schottky and gate controlled power diodes, by including a vertical superjunction region having alternating P and N doped regions for connecting an anode on one surface with a cathode on an opposing surface.
BRIEF SUMMARY OF THE INVENTION
In accordance with the invention, a two-terminal power rectifier, such as a Schottky or gate controlled diode, is provided with a conductive channel having alternating P and N doped regions between the two terminals. The alternating doped regions enhance the reverse bias breakdown voltage while maintaining a low on resistance between the two terminals. The connective channel can have stripped P and N doped regions or meshed P and N regions.
The invention and objections and features thereof will be more readily apparent from the following detailed description and the appended claims when taken with the drawings.
REFERENCES:
patent: 3603811 (1971-09-01), Day
patent: 4373252 (1983-02-01), Caldwell
patent: 4754310 (1988-06-01), Coe
patent: 4982260 (1991-01-01), Chang et al.
patent: 4996581 (1991-02-01), Hamasaki
patent: 5162876 (1992-11-01), Kitagawa et al.
patent: 5216275 (1993-06-01), Chen
patent: 5430315 (1995-07-01), Rumennik
patent: 5438215 (1995-08-01), Tihanyi
patent: 5594261 (1997-01-01), Temple
patent: 5629536 (1997-05-01), Heminger et al.
patent: 5643809 (1997-07-01), Lien
patent: 5747841 (1998-05-01), Ludikuize
patent: 5751025 (1998-05-01), Heminger et al.
patent: 5818084 (1998-10-01), Williams et al.
patent: 5825079 (1998-10-01), Metzler et al.
patent: 5869380 (1999-02-01), Chang
patent: 5877515 (1999-03-01), Ajit
patent: 5886383 (1999-03-01), Kinzer
patent: 5956582 (1999-09-01), Ayela et al.
patent: 5969400 (1999-10-01), Shinohe et al.
patent: 6034385 (2000-03-01), Stephani et al.
patent: 6037631 (2000-03-01), Deboy et al.
patent: 6066878 (2000-05-01), Neilson
patent: 6081009 (2000-06-01), Neilson
patent: 6097046 (2000-08-01), Plumton
patent: 6186408 (2001-02-01), Rodov et al.
patent: 6225180 (2001-05-01), Fujii
patent: 6235601 (2001-05-01), Kim
patent: 6258634 (2001-07-01), Wang et al.
patent: 6274904 (2001-08-01), Tihanyi
patent: 6313001 (2001-11-01), Johansson et al.
patent: 6323091 (2001-11-01), Lee et al.
patent: 6362036 (2002-03-01), Choizzie et al.
patent: 6448160 (2002-09-01), Chang et al.
patent: 322 040 (1989-06-01), None
patent: 406061250 (1993-03-01), None
patent: 405082534 (1993-04-01), None
patent: 405175206 (1993-07-01), None
patent: 406112149 (1994-04-01), None
Cezac et al., “A New Generation of Power Unipolar Devices: the Concept of the Floating Islands MOS Transistor (FLIMOST),”Proc. of ISPSO 2000, pp. 69-72, conference held May 22-25, 2000 in Toulouse France (2000).
Christiansen, B., “Synchronous Rectification Improves with Age,”PCIM, pp. 1-6 (1998).
Daniel et al., “Modeling of the CoolMOS™ Transistor—Part I: Device Physics,”IEEE Transactions on Electron Devices, 49(5):916-922 (2002).
Daniel et al., “Modeling of the CoolMOS™ Transistor—Part II: DC Model and Parameter Extraction,”IEEE Transactions on Electron Devices, 49(5):923-929 (2002).
Fujishima et al., “A High Density, Low On-resistance, Trench Lateral Power MOSFET with a Trench Bottom Source Contact,”Proc. 2001 Symp. on Power Semiconductor Devices and IC's, pp. 143-146, held in Osaka Japan (2001).
Gan et al., “Poly Flanked VDMOS (PFVDOS): A Superior Technology for Superjunction Devices,”IEEE, pp. 2156-2159 (2001).
Huang et al., “Characterization of Paralleled Super Junction MOSFET Devices under Hard- and Soft-Switching Conditions,”IEEE, pp. 2145-2150 (2001).
Kim et al., “Minimization of reverse Recovery Effects in Hard-Switched Inverters using CoolMOS” Power Switches,IEEE, pp. 641-647 (2001).
Kim et al., “A Novel Process Technique for Fabricating High Reliable Trench DMOSFETs using Self-Align Technique and Hydrogen Annealing,”Proc. 2001 Int. Symp. on Power Semiconductor Devices and ICs, pp. 139-142, held in Osaka Japan (2001).
Minato et al., “Which is cooler, Trench or Multi-Epitaxy?,”Proc. of ISPSO 2000, pp. 73-76, conference held May 22-25, 2000 in Toulouse France (2000).
Nitta et al., “Experimental Results and Simulation Analysis of 250V Super Trench Power MOSFET (STM),”Proc. of ISPSO 2000, pp. 77-80, conference held May 22-25, 2000 in Toulouse France (2000).
Saggio et al., “MDmesh™: innovative technology for high voltage PowerMOSFETs,”Proc. of ISPSO 2000, pp. 65-68, conference held May 22-25, 2000 in Toulouse France (2000).
Shimizu et al., “100V Trench MOS Barrier Schottky Rectifier Using Thick Oxide Layer (TO-TMBS),”Proc. 2001 Int. Symp. on Power Semiconductor Devices and ICs, pp. 243-246, held in Osaka Japan (2001).
Udrea et al., “Ultra-high voltage termination using the 3D RESURF (Super-Junction) concept—experimental demonstration at 6.5 kV,”Proc. 2001 Int. Symp. on Power Semiconductor Devices and ICs, pp. 129-132, held in Osaka Japan (2001).
Zhang et al., “Forward and Reverse Biased Safe Operating Areas of the COOLMOS™,”IEEE, pp. 81-86 (2000).
Zhang et al., “Analysis of the Forward Biased Safe Operating Area of the Super Junction MOSFET,”Proc. of ISPSO 2000, pp. 61-64, conference held May 22-25, 2000 in Toulouse France (2000).
Bao Jianren
Chang Paul
Chern Geeng-Chuan
Chiang Arthur Ching-Lang
Hsueh Wayne Y. W.
APD Semiconductor, Inc.
Beyer Weaver & Thomas LLP
Luu Chuong A
Smith Matthew
LandOfFree
Power diode having improved on resistance and breakdown voltage does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Power diode having improved on resistance and breakdown voltage, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power diode having improved on resistance and breakdown voltage will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3364745