Power delivery package having through wafer vias

Details Power delivery package having through wafer vias Power delivery package having through wafer vias

2007-03-15

2009-11-10

Lee, Calvin (Department: 2892)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C257S774000

Reexamination Certificate

active

07615487

ABSTRACT:
An integrated circuit chip package and a method of manufacture thereof are provided. In one embodiment, the integrated circuit chip package comprises a semiconductor die having power and ground routings, a plurality of through wafer vias disposed within the semiconductor die, the through wafer vias connected to the power and ground routings, and a substrate attached to the semiconductor die, the substrate having power and ground leads connected to the through wafer vias for transferring power from the substrate to the semiconductor die.

REFERENCES:
patent: 6924551 (2005-08-01), Rumer et al.
patent: 6967556 (2005-11-01), Gaschke et al.
patent: 2005/0184390 (2005-08-01), Gagne et al.
patent: 2007/0176281 (2007-08-01), Kim et al.
patent: 2007/0220207 (2007-09-01), Black et al.
patent: 2008/0179758 (2008-07-01), Wong et al.
patent: 2006-228897 (2006-08-01), None

Affiliated with

Also associated with

Rating

Power delivery package having through wafer vias does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Power delivery package having through wafer vias, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power delivery package having through wafer vias will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4088270