Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2002-08-27
2004-09-21
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S227000, C365S228000, C365S229000
Reexamination Certificate
active
06795362
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for controlling power for a semiconductor storage device having a memory cell which must be refreshed to maintain data and the semiconductor storage device employing the method for controlling power.
The present application claims priority of Japanese Patent Application No. 2001-256913 filed on Aug. 27, 2001, which is hereby incorporated by reference.
2. Description of the Related Art
FIG. 13
is a block diagram showing an example of configurations of a conventional semiconductor storage device having a memory cell which must be refreshed to maintain data. The conventional semiconductor storage device is a DRAM (Dynamic Random Access Memory) having a storage capacity of 64 Mbits and is made up of four banks and having a number of refresh processes denoting a number of rows in each of memory cell arrays
11
1
to
11
4
activated by one time refresh process being 4096 (=2
12
). The conventional semiconductor storage device chiefly includes four pieces of banks
1
1
to
1
4
, column decoder groups
2
1
to
2
4
, row decoder groups
3
1
to
3
4
, an input buffer
4
, an output buffer
5
, a multiplexer (MUX)
6
, a command decoder
7
, a row column address buffer
8
, a refresh counter
9
, and a self-refresh circuit
10
.
Each of the banks
1
1
to
1
4
includes each of the memory cell arrays
11
1
to
11
4
and each of sense amplifiers/input and output buses (SA-IOB)
12
1
to
12
4
. Each of the memory cell arrays
11
1
to
11
4
has a storage capacity of 16 Mbits in which a plurality of pieces of memory cells is arranged in a matrix form. Each of sense amplifiers (SAs) making up each of the SA-IOB
12
1
to
12
4
detects data read from a memory cell on a column of corresponding memory cell arrays
11
1
to
11
4
being selected by a row decoder making up the corresponding row decoder groups
3
1
to
3
4
to a bit line and amplifies the detected data. Each of the input/output buses (IOBs) making up each of the SA-IOBs
12
1
to
12
4
, while being connected to a global input/output bus
13
, at a time of reading data, transmits data detected and amplified by each of the corresponding SAs to the global input/output bus
13
while, at a time of writing data, transmits the data transmitted by the global input/output bus
13
to a memory cell selected out of the corresponding memory cell arrays
11
1
to
11
4
.
Each of the column decoder groups
2
1
to
2
4
is mounted on each of the banks
1
1
to
1
4
and has a plurality of column decoders. Each of the column decoders operates to decode a column address fed from a row column address buffer
8
and outputs a plurality of column selection switching signals used to put each of the SAs being connected to corresponding bit lines of each of memory cell arrays
11
1
to
11
4
into a selection state. Each of the row decoder groups
3
1
to
3
4
is mounted on each of the banks
1
1
to
1
4
and has a plurality of row decoders. Each of the row decoders decodes a row address fed from the row column address buffer
8
and puts a corresponding word line of each of the memory cell arrays
11
1
to
11
4
into the selection state.
The input buffer
4
being connected commonly to the banks
1
1
to
1
4
amplifies and buffers data being input a data input/output terminal DQ and then feeds it to the MUX
6
. The output buffer
5
being connected commonly to the banks
1
1
to
1
4
amplifies and buffers data fed from the MUX
6
and outputs sequentially it from the data input/output terminal DQ. The MUX
6
feeds data supplied through the global input and output bus
13
from the IOBs making up the SA-IOB
12
1
to
12
4
to the output buffer
5
and data fed from the input buffer
4
through the global input/output bus
13
to the IOBs making up SA-IOB
12
1
to
12
4
.
The command decoder
7
, when a clock enable signal CKE fed from an external is changed from its high to low level, decodes a chip select signal/Cs, row address strobe signal/RAS, column address strobe signal/CAS, and write enable signal/WE fed in synchronization with a clock CLK fed from an external and, if it is judged that operations are in a self-refresh mode (entry), produces a high-level self-refresh start signal SRT and feeds the row column address buffer
8
and the self-refresh circuit
10
. The self-refresh start signal SRT is used to instruct a self-refresh process to be started. Also, the command decoder
7
produces a row activated signal &phgr; RAS based on a self-refresh signal &phgr; SRF supplied from the self-refresh circuit
10
and feeds it to a row column address buffer
8
. The self-refresh signal &phgr; SRF is an original signal from which the row activated signal &phgr; RAS is produced and is used to set a basic period for the self-refresh process. The row activated signal &phgr; RAS is a basic signal used to activate row-based components such as the row decoder groups
3
1
to
3
4
or a like. Moreover, the clock enable signal CKE is active high while the chip select signal/CS, row address strobe signal/RAS, column address strobe signal/CAS, and write enable signal/WE are all active low.
The row column address buffer
8
, while an ordinary operation is being performed, produces a column address and a row address based on an address AD fed from an external and the row address is fed to a plurality of row decoders making up each of the row decoder groups
3
1
to
3
4
with timing when a row activated signal &phgr; RAS is fed from a command decoder
7
. Also, the row column address buffer
8
, when a self-refresh start signal SRT is fed from the command decoder
7
at a time of the self-refresh process, based on a counter value RCT supplied from the refresh counter
9
, produces a row address for the self-refresh process and, with timing when a row activated signal &phgr; RAS supplied from the command decoder
7
is fed, feeds the row address to the plurality of row decoders making up each of the row decoder groups
3
1
to
3
4
. In the refresh counter
9
, at the time of a self-refresh process, its counter value RCT is updated and the updated counter value RCT is fed to the row column address buffer
8
. The self-refresh circuit
10
, based on a high-level self-refresh start signal SRT supplied from the command decoder
7
, produces a self-refresh signal &phgr; SRF in a period of a clock produced by an oscillator (not shown) mounted therein and feeds it to the command decoder
7
.
Next, internal operations of the semiconductor storage device having configurations described above to be performed at a time of the self-refresh process will be described by referring to a timing chart shown in FIG.
14
. First, the clock enable signal CKE, as shown in
FIG. 14
(
2
), remains high in an initial state before time t
1
and the clock CLK changes to be low in synchronization with a rise of a clock CLK at the time t
2
(see FIG.
14
(
1
)). That is, in the initial state before the time t
1
, an internal state ST of the conventional semiconductor storage device is an idle state IST in which no operation is performed, as shown in FIG.
14
(
4
).
In such the initial state, the clock enable signal CKE (see FIG.
14
(
1
)) changes to be low in synchronization with a rise of a clock CLK at the time t
2
as shown in FIG.
14
(
2
) and, as shown in FIG.
14
(
3
), a command SRC, one of a command CMD, used to instruct setting of a self-refresh mode is fed. The command SRC is fed when, for example, a low-level chip selector signal/CS, low-level row address strobe signal/RAS, low-level column address strobe signal/CAS and high-level write enable signal/WE are supplied in synchronization with the clock CLK. This makes the command decoder
7
decode the low-level chip select signal/CS, low-level row address strobe signal/RAS, low level column address strobe signal/CAS and high-level write enable signal/WE and judges that operations are set to be in a self-refresh mode. Therefore, the command decoder
7
produces a high-level self-refresh start signal SRT shown i
Hashimoto Takeshi
Ito Yutaka
Kato Hideaki
Nakai Kiyoshi
Elpida Memory Inc.
Nguyen Tan T.
Young & Thompson
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