Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Multiple or variable intervals or frequencies
Reexamination Certificate
1998-10-09
2001-07-17
Black, Thomas (Department: 2171)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Multiple or variable intervals or frequencies
C713S600000
Reexamination Certificate
active
06263448
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to power domains, and in particular to clock power domains in memory systems such as dynamic random access memories (DRAMs).
Power consumption is a constraint on computer systems both by virtue of limited power available in portable, battery-operated systems, and also limited heat dissipation for high power devices. As devices are made faster by increasing their clock speed, the power requirements also increase since clock signal lines, receivers, and other clock circuits consume more power and generate more heat as device clock rates increase.
Some memory systems operate asynchronously. Other memory systems, to increase the speed and bandwidth, operate synchronously using a clock signal. For these synchronous systems, clock power becomes an important issue at high frequencies. High power consumption by the clock signal can exceed thermal cooling limits of the package or system or cause excessive battery drain in portable devices.
In a prior Rambus dynamic random access memory (DRAM) system, illustrated in
FIG. 1
, three clock domains are used to control clock power use.
FIG. 1
shows a memory core
11
and a memory interface
13
. A first domain consists of the control circuitry
15
, and a second domain is the write path
17
into the memory core. A third path is read data path
19
. Table 1 indicates which clock domains are on for different power modes. The clock power to all three domains can be turned off in a standby mode. The control domain is turned on to enter an active mode. The write data path
17
is additionally turned on when needed for a write operation, an active write mode. Read data path
19
is turned on for a read operation, an active read mode. In a read operation, the control domain is turned on first, to allow the control signals for the read to be provided to the memory core. Since there will be some delay before the data is available, the output data path for the data to be read need not have its clock turned on until some period of time later. Thus, there is a latency between when the control logic is turned on and provided the clock signal to when the read data output path is turned on.
TABLE 1
Clock Domains
power modes
rclk
sclk
tclk
standby
off
off
off
active
on
off
off
active read
on
off
on
active write
on
on
off
In a prior Rambus system, the read data path is turned on automatically by the control logic when the control logic is activated for a read. Thus, a separate control signal does not need to be sent over the interface to turn on the read data path. A register will store a count corresponding to the latency from a RAS control signal to when read data will be available from the memory core, and this register value is used to control the latency of the clock turn-on for the read data path.
One disadvantage of the prior Rambus system is the additional latency required for turning on the control logic to exit the standby power mode. Since the interface control logic and datapath must be on before an incoming command can be processed and a memory operation started, the turn-on latency of the control logic and datapath directly adds to the memory access latency. This provides a power versus latency trade off.
Another method of limiting clock power consumption is to use a slower clock signal. This is done in microprocessors which have a low power or sleep mode. Typically, these are used in laptop computers in which the user can select a lower power mode, or the laptop will automatically enter the lower power or sleep mode in the absence of any user input within a predefined period of time.
SUMMARY OF THE INVENTION
The present invention provides a memory device with multiple clock domains. Separate clocks to different portions of the control circuitry create different clock domains. The different domains are sequentially turned on as needed to limit the power consumed. The turn on time of the domains is overlapped with the latency for the memory access to make the power control transparent to the user access of the memory core.
In one embodiment, the present invention separates out the RAS control logic into a separate clock domain from the CAS control logic. This smaller amount of RAS control logic can then be left on in a standby power mode to eliminate any visible latency from a RAS signal through to data access.
The write and read data paths are also in separate clock domains to further conserve power depending upon whether an operation is a read or write operation.
In one embodiment, the power control is implicit and transparent to the user. In a standby mode, a RAS signal will cause the control logic associated with the RAS control logic to activate the CAS clock domain an appropriate latency after receipt of the RAS signal without any further control over the memory interface required. When a CAS read or write signal is received, that will implicitly, or automatically, cause the read or write clock domain to be turned on an appropriate latency after the CAS signal.
In yet another embodiment of the invention, the memory device can dynamically switch between a fast and a slow clock depending upon the needed data bandwidth. The data bandwidth across the memory interface can be monitored by the memory controller, and when it drops below a certain threshold, a slower clock can be used. The clock speed can be dynamically increased as the bandwidth demand increases. Thus, rather than a coarse switch between a slow or fast clock speed depending upon user activity, clock speed can be switched automatically depending upon data access bandwidth requirements.
For a further understanding of the nature and advantages of the invention, reference should be made to the following description taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 4528661 (1985-07-01), Bahr et al.
patent: 5432468 (1995-07-01), Moriyama et al.
patent: 5452401 (1995-09-01), Lin
patent: 5471607 (1995-11-01), Garde
patent: 5758132 (1998-05-01), Strahlin
patent: 5793227 (1998-08-01), Goldrian
patent: 5796995 (1998-08-01), Nasserbakht et al.
patent: 5802356 (1998-09-01), Gaskins et al.
patent: 5815693 (1998-09-01), McDermott et al.
patent: 5884100 (1999-03-01), Normoyle et al.
patent: 5918058 (1999-06-01), Budd
patent: 5987620 (1999-11-01), Tran
patent: 6134638 (2000-10-01), Olarig et al.
patent: 94112140 (1994-03-01), None
patent: 96308132 (1996-11-01), None
Mar. 15, 1999, PCT Search Report.
Barth Richard M.
Hampel Craig E.
Stark Donald C.
Tsern Ely K.
Black Thomas
Pennie & Edmonds LLP
Rambus Inc.
Wang Mary
LandOfFree
Power control system for synchronous memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Power control system for synchronous memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power control system for synchronous memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2559329