Power control in a data flow processing architecture

Details Power control in a data flow processing architecture Power control in a data flow processing architecture

2005-08-10

2008-10-14

Perveen, Rehana (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S100000, C713S300000, C345S100000, C327S530000

Reexamination Certificate

active

07437582

ABSTRACT:
Method and system for dynamically adjusting performance of circuitry blocks are described. A first circuit domain is coupled to an interim storage device. The first circuit domain includes a first level shifter coupled to an input of a first circuitry block and a second level shifter coupled to an output of the first circuitry block. The second level shifter is coupled between the output of the first circuitry block and an input of the interim storage device. A controller is coupled to the first circuit domain for adjustment of a first operating voltage of the first circuit domain.

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Lee, Edward A. et al., “Dataflow Process Networks,”Proceedings of the IEEE, May 1995, pp. 773-799, vol. 83, No. 5.

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