Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
1998-09-02
2001-05-15
Saras, Steven (Department: 2675)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C345S211000
Reexamination Certificate
active
06232964
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. §119 from my application entitled Power Control Device for Display Device Having PFC Function filed with the Korean Industrial Property Office on Sep. 2, 1997 and duly assigned Serial No. 97-45465 by that Office.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a computer display device (monitor) and, more particularly, to a power control circuit for such a display device, which utilizes a frequency-controlled oscillator in order to implement a power factor correction (PFC) function while the display device is in a display power management signaling (DPMS) mode.
2. Description of the Related Art
A display device for use with a personal computer is generally manufactured with internal control means for reducing power consumption in accordance with, for example, the DPMS standard. In conformity with the DPMS standard, a host computer, which typically includes a video card, selectively supplies (or blocks) horizontal and vertical sync signals to the display device according to the computer's state of use, which is continually monitored in order to conserve power. Thus, a DPMS function enables the display device to manage its power distribution according to the presence (or absence) of the video sync signals. The power management states are classified into an “on” (normal) state, a standby state, a suspend state and a power-off state.
DPMS
sync signal applied
state
horizontal
vertical
on
yes
yes
standby
no
yes
suspend
yes
no
off
no
no
As shown in the above table, both the horizontal and vertical sync signals are applied to the display device in the “on” state, only the vertical sync signal is applied in the standby state, only the horizontal sync signal is applied in the suspend state, and neither sync signal is applied in the power-off state. Starting in the normal mode, the DPMS state converts, in sequence, first to the standby mode, then to the suspend mode, and finally to the power-off mode, according to a time lapse corresponding to the lack of use of the computer system. In the normal operation mode, a monitor is fully supplied with electric power, while in the stand-by and suspend modes, the display is selectively muted (blanked) to reduce power. In the power-off mode, the supply of power for the monitor is cut off.
Meanwhile, a contemporary display device employs a rectifying circuit to obtain a DC supply power for internal use by rectifying a general-purpose AC voltage. Such a rectifying circuit, however, does not correct for a loss of power incurred due to a phase difference existing between the current and the voltage output by the rectifying circuit. This phase difference is known as a power factor. Therefore, a power factor correction (PFC) circuit is typically employed and a conventional power control circuit for a display device, as shown in
FIG. 1
, includes such circuitry.
Referring to
FIG. 1
, the conventional circuit includes a microcomputer
10
receiving horizontal (H_SYNC) and vertical (V_SYNC) sync signals from a computer main body (not shown) to discriminate a DPMS mode and outputting a control signal to implement a DPMS mode based on the discriminated mode; a rectifier
20
outputting DC power by a full-wave rectification of a general-purpose AC power input to the display device; a power switch
30
selectively applying the output power of the rectifier based on the mode signal output from the microcomputer; a PFC controller
40
, which includes an internal pulse width modulation (PWM) circuit, generating a PWM signal and functioning according to the operation of the power switch
30
; a PFC power circuit
50
using a DC current from the rectifier
20
to generate a power-factor-corrected power output based on the PWM signal output from the PFC controller
40
; a transformer T
1
limiting the DC output of the rectifier in accordance with the operation of the PFC power circuit
50
; and a microcomputer power supply
60
supplying the microcomputer
10
with uninterrupted electrical power, e.g., 5VDC, which is induced via a winding of the transformer's secondary and then rectified by a diode D
1
and charged in a capacitor C
1
.
In the PFC power circuit
50
, a field-effect transistor (FET) Q
1
connected between a drain resistor R
1
and a source resistor R
3
is switched by the PWM output signal of the PFC controller
40
, which is fed to the gate terminal of the FET Q
1
through a gate resistor R
2
. A feedback current from the source terminal of the FET Q
1
is supplied to a current detection terminal in the PFC controller
40
. Thus, a PFC power output is generated through a rectifying diode D
2
and a charging capacitor C
2
.
In the “on” (normal) mode of DPMS operation of a display device incorporating the above power control circuit, the microcomputer
10
receives both the horizontal (H_SYNC) and vertical (V_SYNC) sync signals from a host computer and outputs a mode signal, e.g., a logic high, which enables the PFC function by turning on (closing) the power switch
30
and thereby powering the PFC controller
40
. In doing so, the PFC controller
40
outputs a PWM signal as shown in
FIG. 2A
, which produces a power-factor-corrected output from the PFC power circuit
50
.
However, in a power savings mode such as standby, suspend or off, the PFC function is disabled since the PWM output signal of the PFC controller
40
is inappropriate for a reduced power consumption state. That is, in any power savings mode of DPMS operation of a display device incorporating the above power control circuit, the microcomputer
10
does not receive both sync signals and outputs a mode signal, e.g., a logic low, which disables the PFC function by turning off (opening) the power switch
30
and thereby cutting off the power to the PFC controller
40
. In doing so, the output of the PFC controller
40
, being disabled as shown in
FIG. 2B
, does not switch the FET Q
1
and the power factor of the output of the PFC power circuit
50
is not corrected.
Accordingly, in the conventional art, the PFC function of the power control circuit of a display device is inoperative in DPMS modes such as standby, suspend and off. Therefore, a power control circuit which allows for power factor correction of the power supply of a display device in all states of DPMS operation is needed.
SUMMARY OF THE INVENTION
Accordingly, in order to overcome such drawbacks in the conventional art, it is therefore an object of the present invention to provide a power control circuit for a display device in which a PFC function can be implemented even in any DPMS mode of the display device.
It is another object of the present invention to provide a power control circuit for a display device, which uses a DPMS mode signal output of a microcomputer to control an oscillating frequency of a PFC control circuit by varying a frequency-controlling property, e.g., a capacitance.
It is yet another object of the present invention to provide a power control circuit for a display device, which selects a frequency-controlling element, e.g., a capacitor, according to a DPMS mode signal output of a microcomputer in order to control an oscillating frequency of a PFC control circuit.
Additional features and advantages of the invention will be set forth in the description which follows and, in part, will be apparent from the description, or may be learned through practice of the invention.
To achieve these objects and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, there is provided a power control circuit for use in a display device having a PFC function, including a microcomputer to determine a DPMS mode of the display device by discriminating a sync signal input from a host computer; a rectifier to output DC power by rectifying an AC power input; a PFC controller, having a PWM circuit, to output a PWM signal according to the DPMS mode determined by th
Nelson Alecia D.
Samsung Electronics Co,. Ltd.
Saras Steven
Staas & Halsey , LLP
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