Power consumption reducing apparatus in using no CPU bus system

Details Power consumption reducing apparatus in using no CPU bus system Power consumption reducing apparatus in using no CPU bus system

1995-12-29

1999-04-27

Sheikh, Ayaz R.

Boots, shoes, and leggings

39575002, 39575003, 395560, 364707, G06F 1328

Patent

active

058988793

ABSTRACT:
A bus master (other than the CPU) sends a signal to a bus controller requesting use of the bus. After receiving the bus-use request signal from the bus master, the bus controller sends a hold signal to the CPU to separate the CPU from the bus. The CPU then outputs a hold response signal in response to the hold signal. Upon receiving the hold response signal from the CPU, the bus controller sends a signal to the bus master requesting use of the bus indicating that that bus master can use the bus. The bus controller also sends a signal to a clock signal generator, which lowers the clock speed below a certain threshold or switches it into a stop clock state. Once the bus controller senses that the bus master is finished using the bus, the bus controller stops the above-mentioned signal sent to the bus master indicating that the bus master can use the bus.

REFERENCES:
patent: 4807112 (1989-02-01), Hamasaki
patent: 5471625 (1995-11-01), Mussemann et al.

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