Power consumption management apparatus

Details Power consumption management apparatus Power consumption management apparatus

2002-12-04

2004-08-31

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S320000, C713S322000

Reexamination Certificate

active

06785831

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a power-consumption-management apparatus, and more particularly to a power-consumption-management apparatus for managing the power consumption of a data-processing apparatus such that it is kept at a minimum.
2. Prior Art of the Invention
For digital equipment that is generally controlled by a synchronization clock, the power consumption is proportional to the product of the operation clock frequency and the square of the operating voltage and the scale of the circuitry, however, in recent years, as the scale of the circuitry increases through the use of LSI, there is a need to reduce the accompanying increase of power consumption.
The basic thinking of how to reduce power consumption is to lower the frequency and reduce the operating power of the operation clock, or to reduce the size of the circuitry. To be more precise, in the case of digital equipment comprising a plurality of blocks, controlling the clocks and supply voltage of the peripheral circuit blocks by CPU control, which controls clocks and supply voltage of circuit blocks that do not require operation, is very effective in reducing the power consumption. For example, the operating circuit blocks differ depending on the application or task that is executed by the CPU, so the CPU can effectively control the power consumption by controlling when to supply or stop an operation clock according to operating conditions such as whether a circuit block operates or not.
A method of controlling power consumption is disclosed in Japanese Patent H4-211819, as shown in FIG.
14
.
As shown in
FIG. 14
, an information-processing apparatus comprises a master block or CPU
1
, a slave block or input apparatus
2
such as a keyboard, a graphics apparatus
31
for creating figures and drawings, a memory
4
for storing images and the like, and an output apparatus for displaying the images. Here, the master block or CPU
1
controls the slave block or input apparatus
2
, graphics apparatus
31
, memory
4
and output apparatus
5
, and manages their respective operating state.
For example, when a reproduction instruction and image data to be reproduced having a specified format are input from the input apparatus
2
to the CPU
1
, the CPU
1
sends an input-request signal to the graphics apparatus
31
. After receiving this input request, the graphics apparatus
31
returns a receive signal to the CPU
1
after it becomes capable of receiving the data, and then the CPU
1
transfers the image data to the graphics apparatus
31
.
On the other hand, at the same time that the CPU
1
sends an input request to the graphics apparatus
31
, CPU
1
sets a clock-supply command in the control register
11
(for example it sets it to ‘11’), then, as shown in FIG.
15
(
b
), after receiving this clock-supply command, the clock-control apparatus
12
sets the status signal to ‘1’ to indicate that the graphics apparatus
31
is in the no-wait state. Then, as shown in FIG.
15
(
c
), when this status is received, a second synchronization clock
14
is supplied to the graphics apparatus
31
at period T2 of the this no-wait state.
On the other hand, after the graphics apparatus
31
finishes the required processing, it stores the processed data in the memory
4
. At this time as well, the graphics apparatus
31
inputs an input-request signal to the memory
4
, and after the graphics apparatus receives a corresponding receive signal from the memory
4
, it transfers the data.
When the graphics apparatus
31
enters the no-wait state, the CPU
1
constantly monitors that state, and when it detects that processing by the graphics apparatus
31
has finished, it sets a clock-stop command in the control register
11
(for examples, sets it to ‘00’), or sets a minimum-clock-speed command (for example, sets it to ‘01’). When a clock-stop command is set, after receiving the this clock-supply-stop command, the clock-control apparatus
12
sets the status signal to ‘0’ to indicate that the graphics apparatus
31
is in the wait state, as shown in FIG.
15
(
b
). Then, as shown in FIG.
15
(
c
), when this status is received, the supply of the second synchronization clock
14
to the graphics apparatus
31
is stopped at period T1 and T3 of this wait state.
When the minimum-clock-speed command is sent to the control register
11
, the status of the graphics apparatus
31
is set to the wait state, and the second synchronization clock
14
that is supplied to the graphics apparatus
31
at period T1 and T3 of this wait state shown in
FIG. 15
is set to the minimum frequency (not shown in the figure).
Furthermore, after the CPU
1
activates the graphics apparatus
31
, it can move on to a different process if there is no task to be processed, or the CPU
1
can control the supply of its own clock until processing by the graphics apparatus
31
is finished, and reduce power consumption. Even in this state, the CPU
1
monitors the finish state of the graphics apparatus
31
and when the graphics apparatus
31
finishes, the CPU
1
controls the graphics apparatus
31
and sets it to the wait state.
In this way, the CPU
1
(master) controls the supply of the clock to the slave (graphics apparatus
31
) while at the same time monitors the status of the slave, and reduces the power consumption of the information-processing apparatus.
However, with the construction described above, the CPU
1
determines whether or not to supply a clock depending on whether or not the graphics apparatus
31
has finished a series of processes, so the following problems occur.
That is, even though the graphics apparatus
31
sends an input-request signal to the memory
4
, and even though the status is not to receive a receive signal, or in other words, even though the graphics apparatus
31
is not actually operating, the CPU
1
regards the graphics apparatus
31
as operating, so the clock-supply command that is set in the control register
11
keeps the same status. Therefore, even though the clock is not actually necessary, the second synchronization clock
14
is supplied to the graphics apparatus
31
, and power loss occurs.
As the size of the circuitry becomes larger, the CPU
1
cannot sufficiently control the supply of the clocks, and further loss occurs.
In other words, for a data-process apparatus, for example a graphics apparatus
31
, a parallel-processing circuit, such as a pipeline, is often used, however, by doing so, the size of the circuitry of the graphics apparatus
31
increases according to the number of parallel circuits, and in the case of a pipeline, the input data are processed and output sequentially at each stage of the pipeline, so response delays occur according to the number of stages of the pipeline.
In the case of using prior clock control, it is possible to control the clocks for the entire block of parallel processing circuits, however, in the case of a pipeline or the like which performs mutual transfer of data, controlling the clocks for only part of a circuit block becomes difficult. Therefore, as the use of parallel-processing circuits increases, the graphics apparatus
31
, which comprises parallel-processing circuits, consumes a proportional amount of power.
Furthermore, by arranging the graphics apparatus
31
in parallel by using pipeline construction for example, response delays occur as described above according to the number of pipeline stages, so even though processing in an early stage of the pipeline is finished, the CPU
1
cannot perform control to stop the clock supply until processing in each stage of the pipeline is finished. Therefore, further power loss occurs.
As described above, in the prior clock control, when the circuitry is arranged in parallel in order to increase speed, a problem existed in that it was difficult to perform detail power control through monitoring by the master or CPU.
SUMMARY OF THE INVENTION
The object of this invention, proposed based on the problems of the prior art described above, is to provide a power-consumpti

Affiliated with

Also associated with

Rating

Power consumption management apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Power consumption management apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power consumption management apparatus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3320785