Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
2000-10-04
2004-06-01
Lee, Thomas (Department: 2115)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C713S502000, C709S224000
Reexamination Certificate
active
06745335
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multiprocessor system, and more particularly a power consumption control apparatus, a power consumption control method and a recording medium recording thereon a power consumption control program for power saving.
2. Description of the Related Art
A multiprocessor system, being composed of a plurality of processors, tends to be power consuming. Whereas distributed processing is performed in a multiprocessor system by a plurality of processors when the load on the processors is heavy, there is no need to involve all the processors in distributed processing when the load is light. Therefore, having all the processors operate when the load is light would mean wasteful power consumption.
For this reason, techniques to reduce power consumption in such situations are already known according to the prior art, including what is described in the Japanese Patent Application Laid-open No. Hei 5-257907. This technique uses, among other things, two processors and a circuit to control the supply and cut-off of clocks to these processors. Software monitors the load on the processors and, when the load is found to be lighter than a certain level, the supply of clocks to one of the processors is stopped to thereby save the consumption of power.
Therefore, according to the prior art, the load on the processors is monitored by software. However, this load monitoring imposes an extra processing load on the processors, resulting in the problem of an increased overall load on the processors.
SUMMARY AND OBJECTS OF THE INVENTION
An object of the present invention, therefore, is to eliminate the additional load on the processors imposed by the monitoring need, and to efficiently control the consumption of power according to the level of load on the processors.
A power consumption control apparatus in a first multiprocessor system according to the invention is provided with a load monitoring means for monitoring any drop or rise in the loads on the processors, and a processor degenerating/adding means for degenerating part of the plurality of processors when a drop in load is detected by the load monitoring means and suspending the supply of power to the degenerated processor(s) and, when a rise in load is detected, resuming the supply of power to the degenerated processor(s) to add the processor(s) to the multiprocessor system.
A power consumption control apparatus in a second multiprocessor system according to the invention is a variation of the power consumption control apparatus in the first multiprocessor system, wherein the load monitoring means is provided with a first detecting means for detecting a drop in the loads on the processors by the lapse of a first fixed length of time; a second detecting means for detecting a rise in the loads on the processors by the lapse of a second fixed length of time; and an interruption generating means for generating interruption to the processor(s) when either the first detecting means or the second detecting means detects either a drop or a rise in load.
A first power consumption control method for a multiprocessor system having a plurality of processors according to the invention comprises a load monitoring step to monitor any drop or rise in the loads on the processors, and a processor degenerating/adding step to degenerate part of the plurality of processors when a drop in load is detected at the load monitoring step and to suspend the supply of power to the degenerated processor(s) and, when a rise in load is detected, to resume the supply of power to the degenerated processor(s) to add the processor(s) to the multiprocessor system.
A second power consumption control method for a multiprocessor system having a plurality of processors according to the invention comprises a first detecting step to detect a drop in the loads on the processors by the lapse of a first fixed length of time; a second detecting step to detect a rise in the loads on the processors by the lapse of a second fixed length of time; an interruption generating step to generate interruption to the processor(s) when either a drop or a rise in load is detected at either the first detecting step or the second detecting step; and a processor degenerating/adding step, actuated by interruption at the interruption generation step, to degenerate part of the plurality of processors when a drop in load occurs and to suspend the supply of power to the degenerated processor(s) and, when a rise in load occurs, to resume the supply of power to the degenerated processor(s) to add the processor(s) to the multiprocessor system.
A first recording medium for a multiprocessor system having a plurality of processors according to the invention records thereon a program for carrying out load monitoring to monitor any drop or rise in the loads on the processors, and processor degeneration/addition to degenerate part of the plurality of processors when a drop in load is detected by the load monitoring and to suspend the supply of power to the degenerated processor(s) and, when a rise in load is detected, to resume the supply of power to the degenerated processor(s) to add the processor(s) to the multiprocessor system.
A second recording medium for a multiprocessor system having a plurality of processors according to the invention records thereon a program for first detection to detect a drop in the loads on the processors by the lapse of a first fixed length of time; second detection to detect a rise in the loads on the processors by the lapse of a second fixed length of time; interruption generation to generate interruption to the processor(s) when either a drop or a rise in load is detected by either the first detection or the second detection; and processor degeneration/addition, actuated by interruption at the interruption generation, to degenerate part of the plurality of processors when a drop in load occurs and to suspend the supply of power to the degenerated processor(s) and, when a rise in load occurs, to resume the supply of power to the degenerated processor(s) to add the processor(s) to the multiprocessor system.
REFERENCES:
patent: 5737615 (1998-04-01), Tetrick
patent: 5913068 (1999-06-01), Matoba
patent: 6141762 (2000-10-01), Nicol et al.
patent: 5-257907 (1993-10-01), None
Lee Thomas
NEC Corporation
Wang Albert
LandOfFree
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