Power conservation techniques for a digital computer

Details Power conservation techniques for a digital computer Power conservation techniques for a digital computer

2005-09-29

2008-03-04

Patel, Nitin C. (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

C713S320000, C713S322000, C713S323000, C713S324000, C710S036000, C710S059000, C711S100000, C711S163000

Reexamination Certificate

active

07340621

ABSTRACT:
A computer capable of playing real time applications includes a processing circuit configured to operate in a first power state, a second power state, and a third power state where the processing circuit consumes less power in the second state than in the first state, and less power in the third state than in the second state; and a real time subsystem coupled to the processing circuit, wherein the real time subsystem includes a buffer. The buffer is further configured to store data and output the data to an output device thereby enabling the processing circuit to enter the third power state while the buffer is outputting said data.

REFERENCES:
patent: 6266776 (2001-07-01), Sakai
patent: 6360327 (2002-03-01), Hobson
patent: 6499102 (2002-12-01), Ewertz
patent: 6775784 (2004-08-01), Park

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