Electrical computers and digital processing systems: support – Computer power control – Power conservation
Patent
1996-06-18
1999-11-09
Sheikh, Ayaz R.
Electrical computers and digital processing systems: support
Computer power control
Power conservation
713320, G06F 100
Patent
active
059833564
ABSTRACT:
A method and apparatus is disclosed for controlling the application of a clock stopping signal in a processor to limit power consumption. The system controller receives addresses, signals indicative of primary and secondary system activity, and at least one nap timeout signal. Interrupt addresses or programmed addresses are trapped and stored as shadowed addresses. Current addresses may be compared with shadowed addresses. Matching addresses trigger a nap mode. Upon nap mode triggering, the clock stopping signal may be applied during a throttling period. Applying the clock stopping signal with programmable duty cycle during the throttling period ensures that processing necessary for the detection and servicing of primary and secondary activity can occur. A prefetch detect circuit ensures that shadowed addresses loaded in the middle of a prefetch do not trigger the clock stopping signal. Clock stopping signal is removed or inhibited when primary or secondary activity is detected or when a nap timer expires.
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Jiang Leo
Ma Kenneth
Pandey Vimi
Shaw Scott
National Semiconductor Corporation
Pancholi Jigar
Sheikh Ayaz R.
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