Electricity: electrical systems and devices – Electrostatic capacitors – Fixed capacitor
Reexamination Certificate
1999-01-08
2001-05-01
Dinkins, Anthony (Department: 2831)
Electricity: electrical systems and devices
Electrostatic capacitors
Fixed capacitor
C361S321300, C361S313000, C257S532000
Reexamination Certificate
active
06226171
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to power conducting substrates having one or more capacitor structures formed therein and methods for making the same. More particularly, the present invention is related to the fabrication of such capacitors for Multichip Modules and the like where the substrates extend over large areas.
BACKGROUND OF THE INVENTION
As the clock rates and the IC density increase in multichip modules (MCMs), power supply noise becomes a more serious problem. It becomes more desirable to position decoupling capacitors closer to the chips and therefore to more effectively isolate the active devices from the switching transients because of the reduced inductance that comes with closer positioning. Approaches to accomplish this include either incorporating a thin film capacitor structure into the multichip module as an integral capacitor or placing the decoupling capacitors between the chip and multichip module, such as on interposer substrates.
One drawback of using decoupling capacitors disposed on interposer substrates is that the amount of chip assembly is doubled. Another drawback is that the chances of solder bump failure can be doubled. A thin film capacitor which is integrated into the body of the multichip module would not have these drawbacks, and therefore is appealing. However, the manufacturing of integrated thin film capacitors faces several technological hurdles before these capacitors can be reliable and economical.
One of these issues is that the integral capacitor needs to be compatible with the dielectric and metal layers used in the multichip module, and with the processing steps used to form these layers. Therefore, the processing conditions and temperatures used to fabricate the integrated capacitor must not degrade the dielectric and metal layers, and, conversely, the integrated capacitor must have sufficient thermal stability such that its electrical characteristics are not degraded by the formation of the dielectric and metal layers. For example, the formation of a conventional copper-polyimide multichip module requires that each polyimide layer be cured at a high temperature of 300° C. to 450° C. for 30 minutes to 2 hours, depending on the thickness and chemical composition of the polyimide layer, which would expose an integrated capacitor structure to several extended periods at high temperature. These issues have been addressed by Applicants' co-pending U.S. patent application Ser. No. 08/826,980, now U.S. Pat. No. 5,872,696 entitled “SPUTTERED AND ANODIZED CAPACITORS CAPABLE OF WITHSTANDING EXPOSURE TO HIGH TEMPERATURES,” assigned to the same assignee of the present application, and incorporated herein by reference.
As another technological hurdle to be addressed, because the integrated capacitor is formed over a large area, defect density of the thin film integrated capacitor is an important characteristic and must be reduced to increase reliability and manufacturing yields. Furthermore, the capacitor should have as high a capacitance value as possible to be the most effective, which requires the use of a high dielectric constant material and/or the use of a very thin dielectric layer. Unfortunately, the use of thin dielectric layers significantly increases defect densities. Applicants' above-identified U.S. patent application has addressed these issues in a manner which enables substrate capacitors using anodized dielectric to be manufactured reliably and inexpensively. The use of an anodization material to form the capacitor's dielectric layer offers significant advantages over other formation techniques. Such materials generally provide the highest dielectric constants available for capacitor materials, and the anodization process heals many (but not all) types of defects and enables the dielectric layer to be formed in a controlled and uniform manner. A number of inventive features of the present patent application are directed to further structures and procedures which further improved the reliability of the substrate capacitor.
As an additional consideration to constructing substrate capacitors, the series resistance in the electrodes of the integrated capacitor should be kept low to avoid voltage drops across the capacitor during transient current spikes, and to improve transient response time. This consideration complicates the resolution of the above more serious issues by limiting the available options, and may introduce yet additional problems. As an example of such an additional problem, many researchers have tried to construct a capacitor with aluminum (Al) electrodes for good conductivity and a tantalum pentoxide (Ta
2
O
5
) dielectric layer for a high dielectric constant. However, these researchers found that the aluminum chemically reacted with the tantalum pentoxide when the capacitor was heated to 300° C. and significantly increased the leakage current of the capacitor. This issue has been addressed by Applicants' above-identified co-pending U.S. patent application Ser. No. 08/826,980 now U.S. Pat. No. 5,872,696. One inventive feature of this present application complements Applicants' co-pending application by enabling low-impedance connections to the capacitor's bottom electrode to be incorporated into the capacitor structures without substantially impacting the yield of the capacitor structures.
SUMMARY OF THE INVENTION
Broadly stated, a first invention of the present application encompasses a substrate capacitor comprising a base conducting layer, a base insulating layer over the base conductive layer, a plurality of apertures formed through the base insulating layer to the base conducting layer, and a multilayer capacitance structure formed over the base insulating layer and the base conductive layer such that the bottom electrode of the multilayer capacitance structure makes electrical contact to the base conducting layer through the apertures in the base insulating layer. The base conducting layer may comprise a conductive substrate, such as a metal substrate, or may comprise a substrate of any material (e.g., dielectric, semiconductive, metal, etc.) with a top conductive layer formed over it. The base conductive layer provides a low impedance distribution plane for the substrate capacitor. The base insulating layer may comprise any dielectric material; in preferred embodiments it comprises spin-on polyamic acid which is cured to form a polyimide layer. The multilayer capacitance preferably comprises a main dielectric layer which may be formed by anodization and/or cured by anodization, and top and bottom electrode layers which are compatible with the main dielectric layer. In preferred methods of construction, the main dielectric layer is formed by anodization, or is cured by anodization, or is at least partially formed by anodization and is thereafter cured by anodization.
The base insulating layer provides a number of benefits according to the present invention. First, it physically isolates the multilayer capacitance structure from the base conductive layer, which can be a source of defects for the formation of the main dielectric layer (particularly for anodization processes). The base insulating layer tends to cover and encapsulate asperities and defect particles on the base conducting layer, and tends to fill in voids in the surface to provide a very smooth surface for forming the main dielectric layer. Such a smooth surface enables very thin dielectric layers to be reliably made. An anodizable dielectric for the main dielectric layer, which is used in preferred embodiments, provides the benefit of a high dielectric constant, which enables a high capacitance value to be achieved.
In further preferred embodiments, and as a further feature, at least one patch of dielectric material is formed over the bottom capacitance electrode or formed over the main dielectric layer, with each patch being located in the area overlying at least a portion of an aperture in the base insulating layer. The inventors believe that the areas in the multilayer capacitor structure
Beilin Solomon I.
Chou William T.
Lee Michael G.
Ngo David Dung
Peters Michael G.
Coudert Brothers
Dinkins Anthony
Fujitsu Limited
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