Active solid-state devices (e.g. – transistors – solid-state diode – With means to increase breakdown voltage threshold – With physical configuration of semiconductor surface to...
Reexamination Certificate
1999-10-19
2003-06-24
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
With means to increase breakdown voltage threshold
With physical configuration of semiconductor surface to...
C257S168000, C257S488000, C257S491000, C257S510000
Reexamination Certificate
active
06583487
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to vertical power components, and more specifically to an optimization of the voltage breakdown of power components having interconnections on their upper surface.
2. Discussion of the Related Art
FIG. 1
very schematically shows a partial cross-sectional view of a portion of a high voltage power component in a border region thereof. The component, only a portion of which is illustrated, is formed in a lightly-doped silicon substrate
1
. In the following description, it will be assumed that this substrate is of type N but, of course, all conductivity types could be inverted. The component is delimited at its periphery by an insulating wall
2
, which extends from the upper surface to the lower surface of the substrate. The insulating wall can correspond to the limit of the semiconductive chip in which component
1
is formed. It can also correspond, within a semiconductive chip, to a separation between two adjacent components. Of course, the present invention also applies to components of silicon-on-insulator (SOI) type.
In a current configuration of high voltage vertical semiconductor components, a P-type layer
3
is formed, continuously or not, on the lower surface of the substrate and extends to reach the insulating wall. On the upper surface side of the substrate, a layer
4
, also of type P, is arranged. P-type layer
4
, N-type substrate
1
, and P-type layer
3
are layers constitutive of a high voltage vertical component, the high voltage being withstandable especially due to the large thickness and to the small doping level of substrate
1
. PNP layers
4
-
1
-
3
altogether can, for example, form a transistor.
A rear surface metallization M
1
is in contact with the entire rear surface of the component and a metallization M
2
is linked, directly or indirectly, to layer
4
. This link is direct in the case where a PNP transistor is desired to be formed. In the case shown where a thyristor with or without a gate is desired to be formed, an additional heavily-doped N-type layer
5
is made to form the thyristor cathode in contact with metallization M
2
. The periphery of layer
4
is spaced apart from insulating wall
2
by a portion of substrate
1
and further includes, preferably, a lighltly-doped P-type (P
−
) area
6
deeper than region
4
.
When a positive voltage is applied between metalizations M
1
and M
2
, the blocking junction is the junction between substrate
1
and P region
4
-
6
. Around this junction, the breakdown voltage is ensured by a so-called space charge area delimited by equipotential surfaces E
1
L and E
1
H, shown in dotted lines in the drawing. Equipotential surface E
1
L indicates the area at the low potential of electrode M
2
, for example, 0 volt. Equipotential E
1
H designates the area at the high potential of electrode M
1
, for example, 600 volts.
When the device is reverse-biased, that is, metallization M
2
is positively biased with respect to metallization M
1
, the breakdown voltage is essentially ensured by the junction between substrate
1
and, on the one hand, P layer
3
, and on the other hand, insulating wall
2
. E
2
L and E
2
H have been used to designate the limits of the space charge area, that is, the equipotential surfaces at the low potential and at the high potential, respectively. For a device to have a high breakdown voltage, the extreme equipotential surfaces have to be as distant as possible to avoid reaching the semiconductor breakdown potential (on the order of 20 V/&mgr;m). Thus, one of the layers in the vicinity of the junction which ensures the breakdown voltage should be relatively lightly doped so that the space charge area can extend rather widely therein.
Independently from the need to ensure a sufficient breakdown voltage of the component when high potentials are applied thereacross, leakage current problems also arise. For various reasons, for example, due to pollution of the oxides, it is possible for N substrate
1
to be strongly depleted at its surface under an upper insulating layer
8
. An inversion of the population in this region may even be achieved. A channel region ensuring an electric continuity between the external periphery of P region
6
and the internal periphery of insulating wall
2
then appears. To avoid such leakage currents, it is known to use a so-called stop-channel region formed of a heavily-doped N-type (N
+
) area
10
at the surface of substrate
1
between the external periphery of region
6
and the internal periphery of wall
2
. Although this does not appear in cross-section, area
10
actually forms a ring, which extends over the entire periphery of the involved component. Given its high doping level, N
+
ring
10
is not likely to be inverted and thus interrupts any inversion channel likely to form at the component surface. To enhance the equipotentiality of stop-channel ring
10
and avoid the occurrence of a localized depletion, it is conventional to coat this diffused ring
10
with a metallization (not shown).
FIG. 2A
illustrates what can be the effect on the equipotential distribution of a conductive track running over the upper surface of the component. In the example shown, metallization M
2
is prolonged by a metal track L intended, for example, for ensuring a connection between metallization M
2
and a metallization of another component arranged in the same substrate
1
to the right of insulating wall
2
. It should be underlined, given that this is not apparent in the cross-sectional view of
FIG. 2A
, that metallization L corresponds to a relatively thin metal track as compared to the surface occupied by a contact metallization such as metallization M
2
. In power components, the metal track can have a width on the order of 10 to 100 &mgr;m. The way in which equipotential surfaces E
1
L and E
1
H on the one hand and equipotential surfaces E
2
L and E
2
H on the other hand deform, when the component is biased, respectively forward and in reverse, has been shown in FIG.
2
A.
In the case where the component is forward biased, equipotential surface E
1
L is practically not deformed while equipotential surface E
1
H runs along the mechanical track in the direction of insulating wall
2
. When it reaches said insulating wall, a punch-through occurs. This means that the component turns on, while it would be desired for it to be able to withstand the voltage while remaining off. This punch-through is not destructive but causes a premature start of a component which would be desired to remain off.
In a reverse biasing, essentially equipotential surface E
2
L deforms, at the level of the upper component portion. Then, the space charge area reduces and the field at the level of the upper portion of the junction between substrate
1
and wall
2
strongly increases. A breakdown of the junction can occur, which can cause a destruction thereof.
FIG. 2B
shows an alternative of
FIG. 2A
in the case of the presence of a stop-channel region
10
. In a forward biasing, equipotential surfaces E
1
tend to deform as indicated in relation with FIG.
2
A. However, the high equipotential surfaces (EIH) and the intermediary equipotential surfaces will come closer to one another in stop-channel region
10
and there is a high risk for a breakdown to occur in this area. It can thus be seen that the presence of a stop-channel region, which avoids leakage currents, is prejudicial to the breakdown voltage in the considered case.
The problem discussed hereabove, which arises when a connection track runs over a high voltage component, is known in the art and various solutions have been provided to solve it.
An obvious solution consists of increasing the thickness of insulating layer
8
above which conductive track L runs, to reduce the influence on the semiconductor of the field created by this track. However, this solution rapidly comes up against practical limits. Indeed, it is difficult to deposit a high-quality insulator of a thickness greater than 6 &mgr;m which, for oxide, r
Eckert George
Morris James H.
STMicroelectronics S.A.
Wolf Greenfield & Sacks P.C.
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