Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2000-02-15
2002-05-21
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S112000, C327S359000
Reexamination Certificate
active
06392443
ABSTRACT:
FIELD OF INVENTION
The invention relates to digital signaling and more particularly to high frequency preemphasis of a digital signal.
BACKGROUND
In many digital systems, the interconnection bandwidth between chips is a critical limitation on performance. Historically, intra-chip signaling has performed much more slowly than on-chip processing. As technology continues to scale smaller, this bottleneck will become even more pronounced. Without improvements to high speed digital signaling techniques, interchip signaling will prove to be a limit to the technology.
An example of an ideal digital signal
10
is shown in
FIG. 1
a
. A midpoint
12
is shown that serves to define the change in the value of the data bit. In the lower region
10
, the data bit has a value of “0”. While in the upper region
14
, the data bit has a value of “1”. This type of digital scheme with a mid-point
12
is referred to as a single-end signal design.
FIG. 1
b
shows a more realistic view of the waveform of the same digital signal
18
. The midpoint
12
as well as we the upper
14
and lower
16
regions are the same. However, the signals are subjected to some suppression of the signal's peak value called attenuation. The attenuation is particularly pronounced in the case of a single “1” in a field of “0”s. In some instances, the attenuated signal barely reaches the midpoint
12
which results in a very low probability of detection. The attenuation is primarily caused by skin-effect resistance and dielectric absorption by the transmission line. However, the skin-effect resistance is usually the dominant factor. In any case, the magnitude of the attenuation will increase with the frequency.
With a typical broadband signal, the superposition of an unattenuated low frequency signal component with attenuated high frequency signal components causes intersymbol interference that reduces the maximum frequency at which the system can operate. During this intersymbol interference, or hysteresis, the signal “remembers” its previous state. The problem is not so much the magnitude of the attenuation as it is the interference caused by the frequency dependent nature of the attenuation. The interference comes from noise sources such as receiver offset, receiver sensitivity, crosstalk, reflections of previous data bits, and coupled supply noise.
The effects of such interference are shown in
FIGS. 2
a
and
2
b
. Both of these FIGS. show a differential digital signal design. The differential signal differs from the single end signal in that it provides complementary high and low signals instead of a single signal.
FIG. 2
a
shows an attenuated differential signal
20
. The high signal component
22
and the low signal component
24
intersect to form an eye
26
. The amplitude of the eye
28
is obviously dependent on the amount of attenuation of each signal. Only a few decibels (dB) of frequency dependent attenuation can be tolerated by such a signaling system before intersymbol interference overwhelms the signal.
FIG. 2
b
shows a differential signal with deterministic jitter
30
. The amount of offset
32
of jitter affects the width of the eye and may possibly eliminate the eye entirely as shown in
FIG. 2
b
. Jitter is caused by fluctuations in the sampling clock, fluctuations in the receiving clock, and delay variations in the signal path. Each of these sources of jitter are primarily the result of power supply modulation and crosstalk induced delay variation.
One solution to the problem of intersymbol interference is equalization of the signal by pre-emphasizing the high-frequency components of the signal before transmission. This will blue effectively eliminate the interference. The effects of equalization are shown in
FIGS. 3
a
and
3
b
.
FIG. 3
a
shows an unequalized signal that is similar to that shown in
FIG. 2
a
. As shown previously, the amplitude
28
of the eye
26
of the signal is reduced due to the frequency dependent attenuation.
FIG. 3
b
shows a signal
36
where both the high signal component
22
and the low signal component
24
have been equalized. As can be clearly seen, the amplitude
40
of the eye
38
is increased while the full width of the eye
38
is maintained.
Equalization is performed by having a main transmitter and an equalizing duplicate transmitter sum their output currents. The equalizing duplicate transmitter operates with a data bit that is delayed by one clock cycle. A prior art embodiment of a high frequency pre-emphasis circuit is shown in FIG.
4
. An initial data bit
46
(D
N
) is provided as an input to a standard “flip-flop” circuit
44
a
. The flip-flop will output the initial data bit (D
N
) and its complement data bit (D
N
′) upon receiving a clock pulse
48
whereupon a new initial data bit will be provided to the flip-flop
44
a
. Both outputs
50
and
52
are then input into a predriver
54
. Upon receipt of the clock pulse
48
, the output data bit
50
(D
N−1
) is also input into another flip-flop circuit
44
b
. Because this bit is effectively delayed one clock cycle from being input into the second flip flop
44
b
, it is the previous data bit
50
(D
N−1
) from the initial data bit
46
(D
N
). As with the first flip-flop
44
a
, the second flip-flop
44
b
will output the previous data bit
50
(D
N−1
) and the complement previous data bit
52
(D
N−1
′) upon receiving a clock pulse
48
into a second predriver
55
. The outputs of both flip-flops
44
a
and
44
b
are input into two separate predrivers
54
and
55
which each comprise a pass gate multiplexer and a clamping buffer. The output from the predriver
54
for the first flip-flop
44
a
is input into a 10 mnA output stage
56
while the output from the predriver
55
for the second flip-flop
44
b
is input into a 10/4 mA output stage
58
. The outputs from both output stages
56
and
58
are then combined in the output lines
60
.
SUMMARY OF INVENTION
In one embodiment, the invention is a method for pre-emphasizing a digital signal comprising: receiving a data bit as input for a first flip-flop circuit; outputting the data bit and the complement of the data bit from the first flip-flop circuit; receiving a previous data bit from the output of the first flip-flop circuit as input for a second flip-flop circuit; outputting the previous data bit and the complement of the previous data bit from the second flip-flop circuit; receiving the data bit, the complement of the data bit, the previous data bit, and the complement of the previous data bit as input for a predriver; pre-emphasizing a transition in value between the data bit and the previous data bit with the predriver; and outputting an equalized digital signal from the predriver.
The advantages of the disclosed invention may include the use of single drive stage for pre-emphasizing a high frequency signal. This allows for a reduction of power dissipation, a reduction in required area on the chip, and an increase in the bandwidth.
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patent: 4791590 (1988-12-01), Ku et al.
patent: 5300820 (1994-04-01), Sayama et al.
patent: 5396109 (1995-03-01), Oshiba
patent: 5578943 (1996-11-01), Sasaki
patent: 5578944 (1996-11-01), Sasaki
patent: 5787261 (1998-07-01), Osaka et al.
patent: 5887150 (1999-03-01), Schneider et al.
patent: 5923201 (1999-07-01), Suzuki
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Lecture Slides from “Digital Systems Engineering” by W. Dally; Oct. 21, 1998, 10 Pages.
W. Dally and J. Poulton, “Transmitter Equalization for 4Gb/s Signalling”, undated, 10 pages.
J. Poulton, W. Dally and S. Tell, “A Tracking Clock Recovery Receiver for 4Gb/s Signaling”, undated, 13 pages.
W. Dally, M-J. Lee, F-T. An, J. Poulton, and S. Tell, “High Performance Electrical Signaling”, MPPOI98, 1998, 6 pages.
W. Dally, J. Poulton, and S. Tell, slides from presentation: “Multi-gigabit signaling with CMOS”, May 12, 1997, 26 pages.
W. Dally, M-J. Lee, F-T. An, J. Poulton, slides from presentation: “A Small Low-Po
Cho James H.
Rosenthal & Osha L.L.P.
Sun Microsystems Inc.
Tokar Michael
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