Power and signal line bussing method for memory devices

Details Power and signal line bussing method for memory devices Power and signal line bussing method for memory devices

1989-03-31

1991-04-09

Fears, Terrell W.

Static information storage and retrieval

Powering

365 51, G11C 1300

Patent

active

050070258

ABSTRACT:
A memory cell device having circuitry located between memory cell arrays comprises power and ground lines to the circuitry formed directly above the memory cell arrays. The power and ground lines are parallel and positioned in an adjacent alternating pattern such that a power line is positioned adjacent a ground line, which is positioned adjacent another power line and so on. Signal lines carrying signals to and from the circuitry are also formed directly above memory cell arrays.

REFERENCES:
patent: 4426689 (1984-01-01), Henle et al.
patent: 4439841 (1984-03-01), Itoh et al.
patent: 4791609 (1988-12-01), Ito
patent: 4811288 (1989-03-01), Kleijn et al.

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