Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2003-05-16
2004-10-26
Phan, Trong (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S149000
Reexamination Certificate
active
06809953
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a semiconductor device, and in particular to a potential generating circuit, a potential generating device, and a semiconductor device using the same, and a driving method thereof, all of which can provide an electric potential different from a supply voltage.
(2) Description Of Related Art
In recent years, increasingly finer LSIs have been produced. According to a scaling law, a modern MOS transistor has an ultrathin oxide film as a gate insulating film and thus, a supply voltage must be kept low in order to reduce leak current and to maintain and improve reliability. According to a design rule which specifies a minimum gate length of 0.13 [&mgr;m], the oxide film thickness is 1.5 to 1.9 [nm] and the supply voltage is 1.2 to 1.5 [V]. On the other hand, a higher driving force must be provided for the MOS transistor to make a faster circuit and thus a threshold voltage must be reduced. However, a simply reduced threshold voltage may increase the leak current from the MOS transistor on standby.
To solve this problem, several methods of reducing off-leak current have been proposed, e.g., a method of causing the substrate of the MOS transistor on standby to have a negative potential and thus raising the threshold voltage of the MOS transistor. However, it is desirable that a single power supply should be used rather than a plurality of power supplies with different output voltages, since the latter may decrease the degree of circuit integration, lead to a cost increase, or reduce the efficiency. A typical prior art to solve this problem is a charge pump circuit which produces a negative voltage or a raised voltage from a supply voltage.
A substrate bias generating circuit using a prior charge pump circuit pumps up an electric charge out of an output terminal
67
, for example, by causing N-channel MOS transistors
63
and
65
to periodically alternate between the ON state and the OFF state, respectively, as shown in FIG.
12
. This allows the output terminal
67
to become a negative potential. FIGS.
13
(
a
),
13
(
b
), and
13
(
c
) show how the potential &phgr;′ at an input terminal
61
, the potential Vcp′ at an intermediate node
64
, and the potential Vbb′ at the output terminal
67
vary with time, respectively.
With reference to
FIG. 13
, the operation of the prior substrate bias generating circuit will be described below. A pulse signal &phgr;′ with a voltage amplitude of supply potential (Vdd) is applied to the input terminal
61
as shown in FIG.
13
(
a
). When the pulse signal &phgr;′ rises from the ground potential (0) to the supply potential (Vdd), the potential Vcp′at the intermediate node
64
rises from an initial value of −Vtn
2
, as shown in FIG.
13
(
b
), via a charge pump capacitor
62
. The value Vtn
2
indicates the threshold voltage of the N-channel MOS transistor
65
. The potential Vcp′ at the intermediate node
64
rises from the initial value of −Vtn
2
by the value Vdd. When the potential Vcp′ at the intermediate node
64
rises to the potential (−Vtn
2
+Vdd), the N-channel MOS transistor
63
enters the ON state because of an increased gate voltage. This allows the charge pump capacitor
62
to slowly discharge electric charges accumulated in it, while the potential Vcp′ at the intermediate node
64
falls to the threshold voltage Vtn
1
of the N-channel transistor
63
. When the pulse signal &phgr;′ falls from the supply potential to the ground potential, the potential Vcp′ at the intermediate node
64
falls from an initial value of Vtn
1
by the value Vdd. Then, the N-channel MOS transistor
65
enters the ON state, electric charges are accumulated in the charge pump capacitor
62
, and the potential Vcp′ at the intermediate node
64
rises from an initial value of (Vtn
1
−Vdd) to the value −Vtn
2
. In this way, while the N-channel MOS transistor
63
is in the ON state and the N-channel MOS transistor
65
is in the OFF state, electric charges accumulated in the charge pump capacitor
62
are discharged to a grounding terminal, and on the contrary, while the N-channel MOS transistor
63
is in the OFF state and the N-channel MOS transistor
65
is in the ON state, electric charges incoming from the output terminal
67
are accumulated in the charge pump capacitor
62
. The above-described operations are repeated to allow the potential Vbb′ at the output terminal
67
to slowly fall as shown in FIG.
13
(
c
). The finally resultant voltage Vbb′ is expressed by Equation 1 below:
Vbb′=−Vdd
+(
Vtn
1
+
Vtn
2
) (Equation 1)
As described above, if a pulse signal is applied to the input terminal
61
, a negative potential is provided by the charge pump circuit to the output terminal
67
. However, as seen from Equation 1, there is a problem that the absolute value of an output voltage from the prior substrate bias generating circuit may decrease by the sum of the threshold voltages of the N-channel MOS transistors
63
and
65
. Furthermore, it is also a problem that the power efficiency may be as low as approximately 30%.
BRIEF SUMMERY OF THE INVENTION
In order to solve the above-described problems, it is an object of the present invention to provide a potential generating circuit, a potential generating device, and a semiconductor device using the same, and a driving method thereof, all of which can produce no voltage drop in an output voltage.
A first potential generating circuit according to the present invention which can attain the above object comprises: a first capacitor; a second capacitor which is a ferroelectric capacitor connected in series to the first capacitor; an output terminal; a third capacitor for grounding the output terminal; a first switch for connecting a connecting node between the first capacitor and the second capacitor to the output terminal; and a second switch for connecting the connecting node to the ground; wherein during a first period, with the first switch and the second switch placed in the OFF state, a first terminal of the first capacitor opposed to the connecting node is provided with a positive potential and a second terminal of the second capacitor opposed to the connecting node is grounded; wherein during a second period following the first period, the first terminal is grounded and the first switch is placed in the ON state; wherein during a third period following the second period, the first switch is placed in the OFF state, the second switch is placed in the ON state, and the second terminal is provided with a positive potential; wherein during a fourth period following the third period, the second terminal is grounded; and wherein the first through fourth periods are repeated.
A first method of driving a potential generating circuit according to the present invention which can attain the above object comprises: in the above-described first potential generating circuit according to the present invention, a first period during which the first terminal is caused to have a positive potential, the second terminal is grounded, and the first switch and the second switch are placed in the OFF state; a second period following the first period, during which the first terminal is grounded and the first switch is placed in the ON state; a third period following the second period, during which the first switch is placed in the OFF state, the second switch is placed in the ON state, and the second terminal is caused to have a positive potential; and a fourth period following the third period, during which the second terminal is grounded; wherein the first through fourth periods are repeated.
A first potential generating device according to the present invention which can attain the above object comprises: the above-described first potential generating circuit according to the present invention; a control circuit for supplying to the potential ge
Iwata Toru
Kajiwara Jun
Morimoto Kiyoshi
Morita Kiyoyuki
Toyoda Kenji
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