Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2001-03-16
2003-09-02
Nguyen, Minh (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C053S089000, C053S206000
Reexamination Certificate
active
06614270
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a potential detecting circuit and, more particularly, a potential detecting circuit for detecting whether a potential at a predetermined node is higher than a reference potential or not.
2. Description of the Background Art
Conventionally, a dynamic random access memory (hereinbelow, called a DRAM) is provided with a VPP generating circuit for generating a boosted potential VPP higher than an external power supply potential VCC by an amount equal to or higher than a threshold voltage Vthn of an N-channel MOS transistor. The VPP generating circuit is provided with a detector for detecting whether the boosted potential VPP is higher than a target potential or not.
FIG. 15
is a circuit diagram showing the configuration of such a detector
90
. In
FIG. 15
, the detector
90
includes P-channel MOS transistors
91
to
93
, N-channel MOS transistors
94
to
98
, and inverters
99
to
101
. The P-channel MOS transistors
91
and
92
and the N-channel MOS transistors
94
to
96
construct a comparator
102
. The P-channel MOS transistors
91
and
92
are connected between a line of the external power supply potential VCC and nodes N
91
and N
92
, respectively. The gates of the P-channel MOS transistors
91
and
92
are connected to the node N
91
. The P-channel MOS transistors
91
and
92
construct a current mirror circuit. A signal appearing at the node N
92
is an output signal &phgr;C of the comparator
102
. The N-channel MOS transistor
94
is connected between the node N
91
and a node N
96
, and the N-channel MOS transistor
95
is connected between the node N
92
and the node N
96
. The gates of the N-channel MOS transistors
94
and
95
receive a reference potential VR and a partial potential VD, respectively. The partial potential VD is a potential obtained by dividing the boosted potential VPP at a predetermined voltage dividing rate, and is set to reach the reference potential VR when the boosted potential VPP reaches the target potential. The N-channel MOS transistor
96
is connected between the node N
96
and a line of the ground potential GND and its gate receives the external power supply potential VCC. The N-channel MOS transistor
96
serves as a resistive element.
When the partial potential VD is lower than the reference potential VR, a current passing through the MOS transistors
91
,
92
, and
94
is larger than that passing through the N-channel MOS transistor
95
, and the signal &phgr;C is at the “H” level (external power supply potential VCC). When the partial potential VD is higher than the reference potential VR, the current passing through the MOS transistors
91
,
92
, and
94
is smaller than the current passing through the N-channel MOS transistor
95
, and the signal &phgr;C is at the “L” level (source potential VSC of the N-channel MOS transistors
94
and
95
).
The P-channel MOS transistor
93
and the N-channel MOS transistors
97
and
98
construct an inverter
103
. The MOS transistors
93
,
97
, and
98
are connected in series between the line of the external power supply potential VCC and the line of the ground potential GND. Each of the gates of the MOS transistors
93
and
97
receives the signal &phgr;C. A node between the MOS transistors
93
and
97
is an output node N
93
of the inverter
103
. The gate of the N-channel MOS transistor
98
is connected to the drain of the same transistor. The N-channel MOS transistor
98
serves as a diode. The threshold potential of the inverter
103
is set to an intermediate level between the external power supply potential VCC and the source potential VSC of the N-channel MOS transistors
94
and
95
by the N-channel MOS transistor
98
.
When the signal &phgr;C is at the “H” level, the P-channel MOS transistor
93
is nonconductive, the N-channel MOS transistor
97
is conductive, and the node N
93
is at the “L” level (the source potential VSI of the N-channel MOS transistor
97
, that is, the threshold potential Vthn of the N-channel MOS transistor
98
). When the signal &phgr;C is at the “L” level, the N-channel MOS transistor
97
is nonconductive, the P-channel MOS transistor
93
is conductive, and the node N
93
is at the “H” level (external power supply potential VCC).
A signal appearing at the node N
93
is a signal &phgr;EN obtained by being inverted by the inverters
99
to
101
. When the signal &phgr;EN is at the “L” level, the boosted potential VPP is higher than the target potential. When the signal &phgr;EN is at the “H” level, the boosted potential VPP is lower than the target potential. Consequently, by adjusting the boosted potential VPP on the basis of the signal &phgr;EN, the boosted potential VPP can be held at the target potential.
In a semiconductor integrated circuit device such as a DRAM, the size and the power supply voltage of the MOS transistor are being reduced. The reason why the power supply voltage is being reduced is that, as the MOS transistor becomes finer, the withstand voltage of the MOS transistor decreases.
In the detector
90
shown in
FIG. 15
, however, when the external power supply potential VCC decreases, the speed of response of the detector
90
decreases, and the level regulation of the boosted potential VPP becomes large.
The threshold voltage Vthn of the N-channel MOS transistor has negative temperature dependency. The threshold voltage Vthn decreases at high temperature and increases at low temperature. In order to make the N-channel MOS transistor
97
in the inverter
103
conductive, it is therefore necessary to set the level of the signal &phgr;C to 2×Vthn or higher. However, since the threshold voltage Vthn increases at low temperature, the operation margin under the condition of a low power supply voltage is slim.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a detector capable of assuring an operation margin under the conditions of a low temperature and a low voltage.
In a potential detecting circuit according to the invention, an inverter for outputting an inversion signal of an output signal of a comparator includes: a first transistor of a first conduction type connected between a line of a first power supply potential and an output node, having an input electrode for receiving an output signal of the comparator; a second transistor of a second conduction type having a first electrode connected to the output node and an input electrode for receiving an output signal of the comparator; and a third transistor of the second conduction type connected between a second electrode of the second transistor and a line of a second power supply potential, having an input electrode for receiving a predetermined first potential different from a potential of the second electrode of the second transistor. Therefore, the potential of the second electrode of the second transistor can be set to be lower than a threshold potential of the third transistor. Thus, the operation margin under the conditions of a low voltage and a low temperature is made wider than that in the conventional technique.
Preferably, the comparator includes: fourth and fifth transistors of the first conduction type, the fourth transistor being connected between the line of the first power supply potential and a first node, the fifth transistor being connected between the line of the first power supply potential and a second node, each transistor having an input electrode connected to the first node; sixth and seventh transistors of the second conduction type, the sixth transistor being connected between the first and third nodes and having an input electrode for receiving the reference potential, and the seventh transistor being connected between the second node and the third node and having an input electrode for receiving the potential at the predetermined node; and an eighth transistor of the second conduction type connected between the third node and the line of the second power supply potential, having an input electrode for receiving a
Akiyama Mihoko
Fujii Nobuyuki
Morishita Fukashi
Okamoto Mako
Taito Yasuhiko
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Minh
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