Post-silicon control of phase locked loop charge pump current

Details Post-silicon control of phase locked loop charge pump current Post-silicon control of phase locked loop charge pump current

2002-04-24

2003-12-16

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S159000, C331S014000

Reexamination Certificate

active

06664828

ABSTRACT:

BACKGROUND OF INVENTION
As shown in
FIG. 1
, a typical computer system
10
has, among other components, a microprocessor
12
, one or more forms of memory
14
, integrated circuits
16
having specific functionalities, and peripheral computer resources (not shown), e.g., monitor, keyboard, software programs, etc. These components communicate with one another via communication paths
19
, e.g., wires, buses, etc., to accomplish the various tasks of the computer system
10
.
In order to properly accomplish such tasks, the computer system
10
relies on the basis of time to coordinate its various operations. To that end, a crystal oscillator
18
generates a system clock signal (also referred to and known in the art as “reference clock”), SYS_CLK, to various parts of the computer system
10
. Modern microprocessors and other integrated circuits, however, are typically capable of operating at frequencies significantly higher than the system clock, and thus, it becomes important to ensure that operations involving the microprocessor
12
, and the other components of the computer system
10
use a proper and accurate reference of time.
One component used within the computer system
10
to ensure a proper reference of time among a system clock and a microprocessor clock, i.e., “chip clock,” is a type of clock generator known as a phase locked loop, or “PLL”
20
. The PLL
20
is an electronic circuit that controls an oscillator such that the oscillator maintains a constant phase relative to a reference signal. Referring to
FIG. 1
, the PLL
20
has as its input the system clock, which is its reference signal, and outputs a chip clock signal, CHIP_CLK, to the microprocessor
12
. The system clock and chip clock have a specific phase and frequency relationship controlled by the PLL
20
. This relationship between the phases and frequencies of the system clock and chip clock ensures that the various components within the microprocessor
12
use a controlled and accounted for reference of time. When this relationship is not maintained by the PLL
20
, however, the operations within the computer system
10
become non-deterministic.
FIG. 2
shows a PLL
20
. The PLL
20
includes a feedback loop that aligns the transition edge and frequency of a system clock, SYS_CLK
41
, and a feedback loop signal, FBK_CLK
40
. The PLL
20
adjusts the output frequency in order to zero any phase and frequency difference between the system clock
41
and the feedback loop signal
40
. The addition of a divide-by-N stage
39
in the feedback loop enables the PLL
20
to generate an output that has a frequency of N times the system clock
41
frequency. Multiplying the system clock
41
is necessary when a chip clock, CHIP_CLK
42
, must have a higher frequency than the system clock
41
. The PLL core
36
adjusts the output frequency in order to zero any phase and frequency difference between the system clock
41
and the feedback loop signal
40
. By adding the divide-by-N stage
39
, the chip clock
42
must be N times faster to allow the phase and frequency difference between the system clock
41
and the feedback loop signal
40
to zero. The PLL
20
may also have buffers
37
and
38
to drive a larger resistive and/or capacitive load. The buffers
37
and
38
are in the feedback loop so that any phase shift created by the buffers
37
and
38
is zeroed by the PLL core
36
.
One common performance measure for a PLL is jitter. Jitter is the time domain error from poor spectral purity of an output. In other words, in a repeated output pattern, such as a clock signal, a transition that occurs from one state to another does not happen at the same time relative to other transitions. Jitter represents the perturbations that result in the intermittent shortening or lengthening of signal elements of an output. The system clock may have jitter that may need to be filtered by the PLL. The PLL may need to follow and compensate for jitter at the PLL output.
Phase locked loops are basically second order feedback control systems. As such, the phase locked loop can be described in the frequency domain as having a damping factor and natural frequency. The damping factor and natural frequency are fixed by the selection of the PLL circuit parameters. The loop bandwidth is defined as the PLL input frequency at which the PLL output magnitude is 3 dB lower than the PLL output magnitude when the PLL input frequency is zero (DC). The loop bandwidth determines to a large degree the speed at which the phase locked loop can react to a disturbance. The PLL should have a low loop bandwidth so that input clock jitter is filtered. Power supply noise will, however, have a certain noise-versus-frequency characteristic. The PLL loop bandwidth may need to be increased to recover from the generation of output jitter caused by power supply noise.
SUMMARY OF INVENTION
According to one aspect of the present invention, an integrated circuit comprises: a phase locked loop including a phase frequency detector that detects a phase difference between a system clock signal and a feedback clock signal, a charge pump, responsive to the phase frequency detector, that generates a current on a control signal, a bias generator, responsive to the control signal, that generates a bias voltage, and a voltage controlled oscillator, responsive to the bias voltage, that generates an output clock signal; and an adjustment circuit operatively connected to the charge pump, where the adjustment circuit is controllable to adjust the current output from the charge pump.
According to another aspect, a phase locked loop comprises a phase frequency detector that detects a phase difference between a system clock signal and a feedback clock signal; a charge pump, responsive to the phase frequency detector and an adjustment circuit operatively connected to the charge pump, that generates a current signal, where the adjustment circuit is controllable to adjust the current signal; a bias generator, responsive to the current signal, that generates a bias voltage; and a voltage controlled oscillator, responsive to the bias voltage, that generates an output clock signal.
According to another aspect, a method for post-silicon adjustment of a phase locked loop comprises comparing an input clock signal and a feedback clock signal; generating a current signal using a charge pump responsive to the comparing; selectively adjusting the current signal using an adjustment circuit operatively connected to the charge pump; and generating a bias voltage to a voltage controlled oscillator responsive to the current signal, wherein the voltage controlled oscillator generates an output clock signal.
According to another aspect, an integrated circuit comprises: phase locked loop means for generating an output clock signal where the phase locked loop means includes comparing means for detecting a phase difference between an input clock signal and a feedback clock signal (where the feedback clock signal is based on the output clock signal), charge pumping means for generating a current on a control signal (where the charge pumping means is responsive to the comparing means), bias generating means for generating a bias voltage (where the bias generating means is responsive to the control signal), and oscillator means for generating the output clock signal (where the oscillator means is responsive to the bias voltage); and adjusting means for adjusting the current output from the charge pumping means, where the charge pumping means is responsive to the adjusting means.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.


REFERENCES:
patent: 5315270 (1994-05-01), Leonowich
patent: 5668503 (1997-09-01), Gerbach et al.
patent: 6097227 (2000-08-01), Hayashi
patent: 6140881 (2000-10-01), Kim
“Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques” by John G. Maneatis as published in “IEEE Journal of Solid-State Circuits” vol. 31, No. 11, Nov., 1996 (10 pages).

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