Post-passivation thick metal pre-routing for flip chip...

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame

Reexamination Certificate

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C257S678000, C257S686000, C257S690000, C257S700000, C257S738000, C257S778000, C257S780000

Reexamination Certificate

active

06864565

ABSTRACT:
The present invention includes a semiconductor package and a method of making the semiconductor package. The semiconductor package comprises an IC chip and a substrate, wherein part of the substrate routing such as substrate level trace routing is placed on the IC chip using post-passivation thick metal process at wafer level.

REFERENCES:
patent: 6407459 (2002-06-01), Kwon et al.
patent: 20010048591 (2001-12-01), Fjelstad et al.
www.national.com, National Semiconductor Application Note 1126, “BGA (Ball Grid Array)” Dec. 2000, ©2000 National Semiconductor Corporation AN101094.
Intel Technical Notes “Thermal, Electrical and Mechanical Considerations in Applying BGA Technology to a Design”, Dec. 8, 1997, Revision 1.0.
Blankenhorn and Oppert, “A Semi-Additive Electroless Ni/Au Process Offers a Low-Cost Wafer-Bumping Method”, www.chipscalereview.com/issues/0701/techForum01_01.html last visited Oct. 5, 2001.
“Advanced Package Designer High-density IC package design”, www.pcb.cadence.com/pcb/ic/APD.asp last visited Oct. 5, 2001.

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