Post passivation structure for semiconductor chip or wafer

Details Post passivation structure for semiconductor chip or wafer Post passivation structure for semiconductor chip or wafer

2004-02-20

2008-09-02

Louie, Wai-Sing (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S750000, C257S759000, C257SE33062

Reexamination Certificate

active

07420276

ABSTRACT:
The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads for flip chip applications. Photoresist defined electroplating, sputter/etch, or dual and triple damascene techniques are used for forming the metal lines and via fill.

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