Post passivation interconnection schemes on top of the IC chips

Details Post passivation interconnection schemes on top of the IC chips Post passivation interconnection schemes on top of the IC chips

2007-09-21

2008-10-28

Pham, Long (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S690000, C257S700000, C257S774000

Reexamination Certificate

active

07443034

ABSTRACT:
A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

REFERENCES:
patent: 6734563 (2004-05-01), Lin et al.
patent: 2008/0006946 (2008-01-01), Lin et al.
patent: 2008/0042296 (2008-02-01), Lin et al.

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