Semiconductor device manufacturing: process – Making passive device
Reexamination Certificate
2007-10-02
2007-10-02
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Making passive device
C438S393000, C438S239000, C438S240000, C438S250000, C438S622000
Reexamination Certificate
active
11273085
ABSTRACT:
A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
REFERENCES:
patent: 5108950 (1992-04-01), Wakabayashi et al.
patent: 5227012 (1993-07-01), Brandli et al.
patent: 5300461 (1994-04-01), Ting
patent: 5416356 (1995-05-01), Staudinger et al.
patent: 5478773 (1995-12-01), Dow et al.
patent: 5789303 (1998-08-01), Leung et al.
patent: 5929508 (1999-07-01), Delgado et al.
patent: 6030877 (2000-02-01), Lee et al.
patent: 6146958 (2000-11-01), Zhao et al.
patent: 6187680 (2001-02-01), Costrini et al.
patent: 6200888 (2001-03-01), Ito et al.
patent: 6229221 (2001-05-01), Kloen et al.
patent: 6232147 (2001-05-01), Matsuki et al.
patent: 6294425 (2001-09-01), Hideki
patent: 6455885 (2002-09-01), Lin
patent: 6459135 (2002-10-01), Basteres et al.
patent: 6465879 (2002-10-01), Taguchi
patent: 6472745 (2002-10-01), Iizuka
patent: 6495442 (2002-12-01), Lin et al.
patent: 6501169 (2002-12-01), Aoki et al.
patent: 6544880 (2003-04-01), Akram
patent: 6545354 (2003-04-01), Aoki et al.
patent: 6636139 (2003-10-01), Tsai et al.
patent: 6734563 (2004-05-01), Lin et al.
patent: 6759275 (2004-07-01), Lee et al.
patent: 2002/0017230 (2002-02-01), Tahara et al.
patent: 2002/0158334 (2002-10-01), Vu et al.
patent: 2003/0102551 (2003-06-01), Kikuchi
Lee Jin-Yuan
Lin Mou-Shiung
Ackerman Stephen B.
Megica Corporation
Pham Long
Pike Rosemary L. S.
Saile Ackerman LLC
LandOfFree
Post passivation interconnection schemes on top of the IC chips does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Post passivation interconnection schemes on top of the IC chips, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Post passivation interconnection schemes on top of the IC chips will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3869221