Post high voltage gate oxide pattern high-vacuum outgas...

Details Post high voltage gate oxide pattern high-vacuum outgas... Post high voltage gate oxide pattern high-vacuum outgas...

2006-03-28

2006-03-28

Schillinger, Laura M. (Department: 2813)

Semiconductor device manufacturing: process

Chemical etching

C438S725000, C438S687000

Reexamination Certificate

active

07018925

ABSTRACT:
The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region, wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer, and subjecting the exposed nitridated, high voltage dielectric to a high vacuum to remove the accelerant residue.

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