Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1997-12-16
2001-08-28
Chin, Stephen (Department: 2634)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S375000, C375S376000, C327S156000, C327S158000, C327S553000
Reexamination Certificate
active
06282253
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to the field of electronic circuitry and more particularly to a post-filtered recirculating delay-locked loop and method of operation.
BACKGROUND OF THE INVENTION
A recirculating delay-locked loop (DLL) is becoming the system of choice for frequency synthesis where the output frequency is one to twenty times the input frequency. The recirculating delay-locked loop is more desirable than a traditional phase locked loop (PLL) because it provides a first order feedback system as opposed to the typical third or fourth order nature of a phase locked loop. In addition, a recirculating delay-locked loop has better long-term phase noise performance in comparison to a traditional phase locked loop. Furthermore, a delay-locked loop is easy to implement with a digital control that does not require a loop filter. An example recirculating delay-locked loop is described in
A Portable Clock Multiplier Generator Using Digital CMOS Standard Cells
, Michel Combes, Karim Dioury, and Alain Greiner, IEEE Journal of Solid-State Circuits, Vol. 31 No. 7, July, 1996.
A recirculating delay-locked loop utilizes a set of delay elements. The delay elements are adjusted to delay an output clock signal such that the output clock signal has a rising edge coincident with the rising edge of an input clock signal. By providing such delay mechanisms, the input and output clock signals are “locked” into phase with each other. Until an appropriate delay time is automatically determined by the recirculating delay-locked loop for a given input clock signal and output clock signal, any misalignment of phase of the input clock signal and the output clock signal is eliminated by aligning the rising edge of the output clock signal with the rising edge oof the input clock signal once for each clock signal of the input clock.
SUMMARY OF THE INVENTION
The present invention recognizes that a recirculating delay-lock loop may suffer phase discontinuities. The present invention recognizes that a recirculating delay-locked loop can have worse short term, or cycle-to-cycle, phase noise performance in comparison to a phase locked loop because, when an input clock signal and the output clock signal are not “locked,” all phase noise is completely corrected in one cycle of the output clock upon comparison with the input clock. This correction may be referred to as refreshing the phase of the recirculating delay-locked loop. This phase correction occurs once every M cycles, where M is an integer multiple representing the ratio of the frequency of the output clock to the input clock. Correcting this error in one cycle of the output clock can result in an unacceptably large phase discontinuity.
From the foregoing it may be appreciated that a need has arisen for a post-filtered recirculating delay-locked loop and method of operation that eliminates or reduces the problems associated with prior systems. In accordance with the present invention, a post-filtered recirculating delay-locked loop and method of operation are provided that substantially eliminate the disadvantages and problems previously outlined. The present invention utilizes an infinite impulse response filter for smoothing phase discontinuities that occur when a recirculating delay-locked loop refreshes its phase.
According to the present invention, a method for generating a clock signal comprises the steps of receiving a clock signal from a recirculating delay-locked loop, in filtering a periodic output signal from the recirculating delay-locked loop such that any phase shift in the output signal of the recirculating delay-locked loop is spread over a calculated number of periods of the output clock signal to produce a filtered output signal.
According to another aspect of the present invention, an apparatus for producing a clock signal includes a recirculating delay-locked loop operable to receive a reference clock signal, produce an output clock signal, and adjust the relative phase, with respect to the reference clock signal, of the output clock signal to align the output clock signal with the reference clock signal. The apparatus also includes a phase filter that is operable to receive the output clock signal and filter any phase shift of the output clock signal over a plurality of cycles of the output clock to produce an adjusted output clock signal.
The present invention provides a myriad of technical advantages. A post-filtered recirculating delay-locked loop smooths out short term phase discontinuities without giving up the benefit of long term phase performance associated with a recirculating delay-locked loop. The post filtered recirculating delay-locked loop complements the advantages of a first order DLL with a first order infinite impulse response (IIR) post filter (lowpass). The overall behavior of the system remains first order because, according to one embodiment, the output of the filter is not fed back into the recirculating delay-locked loop.
An added advantage of the invention is that it has low bandwidth of reference noise provided that the reference noise is bounded to plus or minus one quarter of an oscillator period while maintaining an effective high bandwidth to noise generated in the loop itself. These two conflicting constraints are conventionally at odds in a traditional PLL. Further, the invention provides noise immunity to the recirculating delay-locked loop, which would otherwise have no noise immunity from a reference clock. Other technical advantages are readily apparent to one skilled in the art from the following figures, description, and claims.
REFERENCES:
patent: 5345119 (1994-09-01), Khoury
patent: 5646564 (1997-07-01), Erickson et al.
patent: 5727037 (1998-03-01), Maneatis
patent: 5790612 (1998-08-01), Chengson et al.
patent: 5796673 (1998-08-01), Foss et al.
Michel Combes et al., A Portable Clock Multiplier Generator Using Digital CMOS Standard, IEEE, Journal of Solid-State Circuits, vol. 31, No. 7, pp. 958-965, Jul. 1996.
Brady W. James
Chin Stephen
Liu Shuwang
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
LandOfFree
Post-filtered recirculating delay-locked loop and method for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Post-filtered recirculating delay-locked loop and method for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Post-filtered recirculating delay-locked loop and method for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2501345