Post exposure bake simulation method

Details Post exposure bake simulation method Post exposure bake simulation method

1998-02-06

1999-12-07

Teska, Kevin J.

G06F 9455

Patent

active

059997206

ABSTRACT:
Disclosed is a post exposure bake simulation method in lithography process to be used for a semiconductor fabrication unit, which has the steps of: expanding an inhibitor concentration distribution to be obtained by exposure calculation according to the boundary condition in the traverse direction; expanding the inhibitor concentration distribution in the depth direction while considering the interface reaction; calculating a Fourier-transformed inhibitor concentration distribution by fast-Fourier-transforming the expanded inhibitor concentration distribution; calculating the Fourier-transform product of the Fourier-transformed inhibitor concentration distribution and the Fourier transform of gaussian distribution; and calculating an inhibitor concentration distribution after diffusion in baking process by inverse-Fourier-transforming the Fourier-transform product by fast-Fourier-transforming.

REFERENCES:
patent: 5621652 (1997-04-01), Eakin
patent: 5717612 (1998-02-01), Capodieci et al.
patent: 5845105 (1998-12-01), Kunikiyo et al.
patent: 5876900 (1999-03-01), Watanaba et al.
patent: 5889678 (1999-03-01), Inouse et al.
Crank, "Methods of solution when the diffusion coefficient is constant" Clarendon Press pp. 11-13 (1975).

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