Post etch silicide formation using dielectric etchback after glo

Details Post etch silicide formation using dielectric etchback after glo Post etch silicide formation using dielectric etchback after glo

1998-04-14

2000-10-31

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438305, 438588, 438593, 438594, H01L 21336, H01L 213205

Patent

active

061402168

ABSTRACT:
The present invention describes the formation of a silicide layer upon a gate conductor by using a masking layer which covers the source/drain regions of the transistor. The method includes forming a masking layer over a semiconductor substrate such that the gate conductor is substantially covered by the masking layer. The masking layer is preferably planarized using any of a variety of well known techniques. After planarization of the masking layer, the masking layer is etched such that an upper surface of the gate conductor is exposed. A silicide layer is preferably formed upon the upper surface of the gate conductor. The masking layer prevents the concurrent formation of silicide upon the source/drain regions.

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