Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-02-12
2004-08-17
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S723000, C438S710000
Reexamination Certificate
active
06777344
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor or integrated circuit manufacture. More particularly, the present invention relates the stripping of photoresist from a wafer during manufacture of the integrated circuit. Still more particularly, the present invention relates to the manufacture of semiconductor devices including at least one layer of organosilicate glass dielectric by stripping the dielectric from the wafer.
BACKGROUND OF THE INVENTION
Integrated circuits use dielectric layers, which have typically been formed from silicon dioxide, SiO
2
, to insulate conductive lines on various layers of a semiconductor structure. As semiconductor circuits become faster and more compact, operating frequencies increase and the distances between the conductive lines within the semiconductor device decrease. This introduces an increased level of coupling capacitance to the circuit, which has the drawback of slowing the operation of the semiconductor device. Therefore, it has become important to use dielectric layers that are capable of effectively insulating conductive lines against such increasing coupling capacitance levels.
In general, the coupling capacitance in an integrated circuit is directly proportional to the dielectric constant, k, of the material used to form the dielectric layers. As noted above, the dielectric layers in conventional integrated circuits have traditionally been formed of SiO
2
, which has a dielectric constant of about 4.0. As a consequence of the increasing line densities and operating frequencies in semiconductor devices, dielectric layers formed of SiO
2
may not effectively insulate the conductive lines to the extent required to avoid increased coupling capacitance levels.
In an effort to reduce the coupling capacitance levels in integrated circuits, the semiconductor industry has engaged in research to develop materials having a dielectric constant lower than that of SiO
2
, which materials are suitable for use in forming the dielectric layers in integrated circuits. To date, a number of promising materials, which are sometimes referred to as “low-k materials”, have been developed. Many of these new dielectrics are organic compounds. In the specification and claims, low-k materials are defined as materials with a dielectric constant k that is less than 3.
Low k materials include, but are specifically not limited to: benzocyclobutene or BCB; Flare™ manufactured by Allied Signal® of Morristown, N.J., a division of Honeywell, Inc., Minneapolis, Minn.; one or more of the Parylene dimers available from Union Carbide® Corporation, Danbury Conn.; polytetrafluoroethylene or PTFE; and SiLK®. One PTFE suitable for IC dielectric application is SPEEDFILM™, available from W. L. Gore & Associates, Inc, Newark, Del. SiLK®, available from the Dow® Chemical Company, Midland, Mich., is a silicon-free BCB.
One interesting class of organic low-k materials is compounds including organosilicate glass, or OSG. By way of example, but not limitation, such organosilicate dielectrics include CORAL™ from Novellus of San Jose, Calif.; Black Diamond™ from Applied Materials of Santa Clara, Calif.; Sumika Film® available from Sumitomo Chemical America, Inc., Santa Clara, Calif., and HOSP™ from Allied Signal of Morristown, N.J. Organosilicate glass materials have carbon and hydrogen atoms incorporated into the silicon dioxide lattice which lowers the dielectric constant of the material.
During semiconductor wafer processing, features of the semiconductor device are defined in the wafer using well-known patterning and etching processes. In these processes a photoresist (PR) material is deposited on the wafer and then is exposed to light filtered by a reticle. The reticle is generally a glass plate that is patterned with exemplary feature geometries that blocked light from propagating through the reticle.
After passing through the reticle, the light contacts the surface of the photoresist material. The light changes the chemical composition of the photoresist material such that a developer can remove a portion of the photoresist material. In the case of positive photoresist materials the exposed regions are removed, and in the case of negative photoresist materials the unexposed regions are removed. Thereafter the wafer is etched to remove the underlying material from the areas that are no longer protected by the photoresist material and thereby define the desired features in the wafer. Low-k organic polymers in general can be etched by oxidation (e.g. oxygen-based) or reduction (e.g. hydrogen-based) chemical processes. OSG dielectrics may be advantageously etched using chemistries somewhat similar to oxide etch chemistries.
The etching of dielectrics may be advantageously accomplished in a dual-frequency capacitively-coupled, (DFC) dielectric etch system. One such is Lam® Research model Exelan HP™, available from Lam® Research Corporation, Fremont Calif. The Exelan HP™ system processes an extremely comprehensive dielectric etch portfolio in one system. Processes include contacts and vias, bi-level contacts, borderless contacts, nitride and oxide spacers, and passivation.
Advanced etch systems like the 4520XL
E
™ perform several processes in the same system. By performing many different semiconductor fabrication steps in a single system, wafer throughput can be increased. Even further advanced systems contemplate the performance of additional steps within the same equipment. Again by way of example, but not limitation, Lam® Research Corporation's Exelan™ system is a dry etch system capable of performing many process steps in a single apparatus. Exelan™ enables hardmask open, inorganic and organic ARC etch, and photoresist strip to be performed in situ with a single chamber. This system's extensive process portfolio includes all dual damascene structures, contacts, vias, spacers, and passivation etch in doped and undoped oxides and low-k dielectrics required in the sub-0.18 micron environment. Of course, the principles enumerated herein may be implemented in wide variety of semiconductor fabrication systems, and these principles specifically contemplate all such alternatives.
As used herein, the term in situ refers to one or more processes performed on a given substrate, such as a silicon wafer, in the same piece of semiconductor fabrication equipment without removing the substrate from the equipment.
During fabrication of a semiconductor device, it is necessary during the repeated patterning, etching, and deposition of the various film layers which make up the device to remove the patterned photoresist following an etching or deposition step. While a number of photoresist removal technologies and methods have been implemented, in order to maintain the high throughput required by today's semiconductor manufacturers, the stripping of photoresist from semiconductor wafers within the etching equipment is highly desirable.
Because OSG materials are basically organically doped oxides, most current photoresist materials tend to have similar chemical characteristics with the organic component of OSG material. In addition, current ex situ processes using an O
2
strip, may use a down stream plasma where a substrate may be heated to temperature above 200° C. Accordingly, when utilizing a known oxygen-based methodology to remove organic material such as photoresist from the cap plate at the wafer's surface, known O
2
strip processes at temperatures above 200° C. have the capability of removing organic material and hydrogen not only from the surface of the wafer, but potentially may also deleteriously remove organic material from the sidewall of the etched feature, or any other exposed surface. Moreover, OSG materials are susceptible to oxidation when exposed to oxygen plasma at high temperatures. The oxygen removes carbon and hydrogen from the OSG film, thereby rendering the films unstable and causing the dielectric constant of the film to increase. Of course, O
2
also provides significantly better strip rates for organic photoresists than most oth
Annapragada Rao V.
Ho Chok W.
Morey Ian J.
Beyer Weaver & Thomas LLP
Elms Richard
Lam Research Corporation
Owens Beth E.
LandOfFree
Post-etch photoresist strip with O2 and NH3 for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Post-etch photoresist strip with O2 and NH3 for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Post-etch photoresist strip with O2 and NH3 for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3307917