Semiconductor device manufacturing: process – Chemical etching
Reexamination Certificate
2000-04-03
2002-04-23
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
C438S691000, C438S692000, C438S697000
Reexamination Certificate
active
06376377
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally chemical mechanical polish (CMP) planarizing methods for forming chemical mechanical polish (CMP) planarized layers within microelectronic fabrications. More particularly, the present invention relates to chemical mechanical polish (CMP) planarizing methods for forming residue free chemical mechanical polish (CMP) planarized layers within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly common within the art of microelectronic fabrication to employ when forming patterned microelectronic conductor layers within microelectronic fabrications, such as but not limited to patterned microelectronic conductor contact layers and patterned microelectronic conductor interconnect layers within microelectronic fabrications, copper containing conductor materials. Similarly, it has also become common in the art of microelectronic fabrication to employ interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications patterned microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials, such as, for example and without limitation, organic polymer spin-on-polymer (SOP) low dielectric constant dielectric materials and silsesquioxane spin-on-glass (SOG) low dielectric constant dielectric materials.
Within the context of the present invention, comparatively low dielectric constant dielectric materials are intended as dielectric materials having a dielectric constant less than about 4.0, more preferably from about 2.0 to less than about 4.0, while for comparison purposes, conventional dielectric materials which may be employed within microelectronic fabrications, such conventional dielectric materials including but not limited to silicon oxide dielectric materials, silicon nitride dielectric materials and silicon oxynitride dielectric materials, typically possess comparatively higher dielectric constants greater than about 4.0, and more typically from greater than about 4.0 to about 8.0.
Copper containing conductor materials are desirable for forming patterned microelectronic conductor layers within microelectronic fabrications since copper containing conductor materials typically possess enhanced electrical properties in comparison with other conductor materials, such as but not limited to aluminum containing conductor materials and tungsten containing conductor materials, which may alternatively be employed for forming patterned microelectronic conductor layers within microelectronic fabrications.
Similarly, low dielectric constant dielectric materials are desirable for forming patterned microelectronic dielectric layers interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications since such low dielectric constant dielectric materials typically provide microelectronic fabrications with enhanced microelectronic fabrication speed and attenuated patterned microelectronic conductor layer cross-talk.
While copper containing conductor materials and low dielectric constant dielectric materials are thus desirable in the art of microelectronic fabrication for forming patterned microelectronic conductor layers having interposed between their patterns patterned microelectronic dielectric layers within microelectronic fabrications, copper containing conductor materials in general, and more particularly in conjunction with low dielectric constant dielectric materials, are not without problems within the art of microelectronic fabrication for forming patterned microelectronic conductor layers having interposed between their patterns patterned microelectronic dielectric layers within microelectronic fabrications. In that regard, insofar as copper containing conductor materials are often difficult to pattern while employing reactive ion etch (RIE) plasma etch methods as are otherwise conventional for forming patterned microelectronic conductor layers within microelectronic fabrications, such patterned microelectronic conductor layers when formed within microelectronic fabrications of copper containing conductor materials are often formed employing damascene methods, including but not limited to dual damascene methods.
As is understood by a person skilled in the art, within a damascene method a blanket copper containing conductor layer is formed into an aperture formed within a patterned microelectronic layer, where the aperture typically comprises a via and/or trench defined within a patterned microelectronic dielectric layer, and the excess of the blanket copper containing conductor layer above the aperture is planarized while employing a chemical mechanical polish (CMP) planarizing method to form within the aperture a chemical mechanical polish (CMP) planarized patterned copper containing microelectronic conductor layer, such as a chemical mechanical polish (CMP) planarized patterned copper containing microelectronic conductor stud layer and/or a chemical mechanical polish (CMP) planarized patterned copper containing microelectronic conductor interconnect layer within the corresponding via and/or the corresponding trench defined by the patterned microelectronic dielectric layer.
While such chemical mechanical polish (CMP) planarizing methods are thus useful for forming within microelectronic fabrications chemical mechanical polish (CMP) planarized patterned copper containing microelectronic conductor layers within microelectronic fabrications, such chemical mechanical polish (CMP) planarizing methods in turn are also not entirely without problems in the art of microelectronic fabrication for forming chemical mechanical polish (CMP) planarized patterned copper containing microelectronic conductor layers having interposed between their patterns patterned microelectronic dielectric layers, such as but not limited to patterned low dielectric constant microelectronic dielectric layers, within microelectronic fabrications. In that regard, it is also known in the art of microelectronic fabrication that a patterned copper containing microelectronic conductor layer, when formed employing a chemical mechanical polish (CMP) planarizing method, is often formed while providing a chemical mechanical polish (CMP) residue layer upon at least a portion of the microelectronic fabrication adjoining the patterned copper containing microelectronic conductor layer. Such a chemical mechanical polish (CMP) residue layer is in turn undesirable in the art of microelectronic fabrication since it often compromises the functionality or reliability of the microelectronic fabrication within which it is formed.
It is thus towards the goal of forming within the art of microelectronic fabrication microelectronic fabrications having formed therein chemical mechanical polish (CMP) planarized patterned copper containing conductor layers having interposed between their patterns patterned low dielectric constant dielectric layers, such as but not limited to chemical mechanical polish (CMP) planarized patterned copper containing conductor stud layers and chemical mechanical polish (CMP) planarized patterned copper containing conductor interconnect layers, having formed interposed between their patterns organic polymer spin-on-polymer (SOP) low dielectric constant patterned dielectric layers and silsesquioxane spin-on-glass (SOG) low dielectric constant patterned dielectric layers, absent chemical mechanical polish (CMP) residue layers formed within the microelectronic fabrication, that the present invention is most specifically directed. In a more general sense, the present invention is also directed towards forming within the art of microelectr
Chang Weng
Chen Ying-Ho
Jang Syun-Ming
Twu Jih-Churng
Ackerman Stephen B.
Perez-Ramos Venessa
Saile George O.
Stanton Stephen G.
Taiwan Semiconductor Manufacturing Company
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