Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2009-05-08
2011-11-15
Tran, Michael (Department: 2827)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S110000
Reexamination Certificate
active
08060696
ABSTRACT:
PET system including array, data processing, and data acquisition. Data acquisition includes one-to-N channel write striping, N-to-one channel read unstriping, N data storage elements, and control logic. Control logic allocates (statically or dynamically) write/read access to data storage elements. Dynamic allocation can be conditional, e.g., that data storage elements be available to receive all input data from array. Embodiments include an input buffer where the condition is determined dynamically based on capacity of the input buffer to temporarily preserve all input data supplied during periods data storage element unavailability. Communication between array and data acquisition can be Fibre Channel simplex implementing only FC-0, FC-1. Data storage elements have data handling bandwidth equal to or greater than (data output rate /N) plus (data input rate/N). Control logic, write striping, read unstriping can be implemented in FPGA. Data storage elements can form a Redundant Array of Independent Disks, e.g., RAID 0.
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Breeding John E.
Everman Jimmy
Jones William F.
Reed Johnny H.
Kendall Peter L.
Siemens Medical Solutions USA , Inc.
Tran Michael
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