Patent
1996-08-28
1999-08-31
Teska, Kevin J.
39550004, 39550009, G06F 1560
Patent
active
059464771
ABSTRACT:
In an automatic positioning/wiring method for a flip-chip semiconductor device which is adapted to design a semiconductor chip including test pads used for inputting/outputting signals in a test, chip terminals respectively arranged on or near the test pads to serve as input/output terminals for an external unit, input/output buffers for exchanging signals with the external unit, and internal circuit blocks which perform predetermined circuit operations in response to signals from the input/output buffers, the internal circuit blocks and the input/output buffers are position/wired in arbitrary regions on the semiconductor chip in an automatic positioning/wiring design process on the basis of a result of a layout position determination process for performing definition such that the input/output buffers and the internal circuit blocks are arranged without discrimination layout regions thereof. A floor plan formation process is performed to arrange the input/output buffers into predetermined groups within the arbitrary region in the form of rows each parallel to one of sides of the semiconductor chip.
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patent: 4835705 (1989-05-01), Fujino et al.
patent: 5208764 (1993-05-01), Rusu et al.
patent: 5293386 (1994-03-01), Mubmenthaler et al.
patent: 5659514 (1997-08-01), Hazani
Do Thuan
NEC Corporation
Teska Kevin J.
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