Position-selective and material-selective silicon etching to...

Details Position-selective and material-selective silicon etching to... Position-selective and material-selective silicon etching to...

1999-03-25

2003-01-14

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

C438S010000, C438S011000

Reexamination Certificate

active

06507044

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit manufacturing and more particularly to position-selective and material-selective etching of silicon.
2. Description of the Relevant Art
Fabrication of an integrated circuit is a complex process involving numerous steps. To form a metal-oxide-semiconductor (MOS) transistor, for example, a gate dielectric is formed on a semiconductor substrate which is doped with either n-type or p-type impurities. A gate conductor is formed over the gate dielectric, and dopant impurities are introduced into the substrate to form a source and drain. Such transistors are connected to each other and to terminals of the completed integrated circuit using conductive interconnect lines.
A pervasive trend in modem integrated circuit manufacture is to produce transistors having feature sizes as small as possible. Many modem day processes employ features, such as gate conductors and interconnects, which have less than 0.3 &mgr;m critical dimension. As feature size decreases, the sizes of the resulting transistors as well as those of the interconnects between transistors also decrease. Fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area.
This trend toward reduced feature sizes imposes severe demands on the reliable operation of the resulting transistors or other electronic devices. Reduction of feature sizes necessitates a “scaling” down of many device dimensions. As gate conductor widths decrease, for example, other transistor dimensions must also decrease in order to maintain proper transistor operation. Early MOSFET scaling techniques involved decreasing all dimensions and voltages by a constant scaling factor, to maintain constant electric fields in the device as the feature size decreased. This approach has given way to more flexible scaling guidelines which account for operating characteristics of short-channel devices. For example, a maximum value of MOSFET subthreshold current can be maintained while feature sizes shrink, by decreasing any or all of several quantities, including gate oxide thickness, operating voltage, depletion width, and junction depth, by appropriate amounts. Such reductions in device dimensions greatly increase the manufacturing accuracy required to form devices which operate properly.
One area of a modem transistor at risk for reliability problems is the gate dielectric. Gate dielectric thicknesses are continually decreasing, driven in part by the device scaling described above. The increased transistor drive current which can be achieved with thinner gate dielectrics is another reason for decreases in gate dielectric thickness. Current gate dielectric thicknesses are therefore typically a few tens of angstroms, or less. Such thin dielectric films are susceptible to breakdown when subjected to the electric fields applied across the gate dielectric during transistor operation. Pinholes or thickness nonuniformities occurring in the gate dielectric are especially likely to cause dielectric breakdown.
Other areas of a transistor in which reliability problems may occur are the contacts made to silicon-based portions of the transistor. The source and drain of the transistor are junctions formed in a silicon substrate, and the transistor gate is typically formed from polycrystalline silicon, or polysilicon. To help in forming a low-resistance contact to such a source, drain or gate region, a metal silicide is often formed on the upper surface of the region. Such a silicide is formed by depositing a metal, typically titanium or cobalt, over the surface of the silicon on which the silicide is to be formed. The substrate is then heated so that the metal reacts with underlying silicon to form a silicide. Modem transistors employ increasingly shallow source and drain junctions to comply with scaling requirements. It is therefore important in many applications that the thickness of a silicide formed at the surface of such a junction be controlled so that the silicide does not extend down through the entire source or drain region, causing a short circuit of the source or drain to the substrate. A high degree of control over the silicide formation process is therefore required.
In order to maintain reliable circuit operation and acceptable yields of working circuits in light of the problems which may be caused or exacerbated by shrinking feature sizes, the ability to carefully examine device structures is important. The device structures examined may be actual devices at various stages of manufacture, or may be test structures used to optimize particular subprocesses involved in the fabrication. Actual imaging of the device structures examined is particularly desirable in many cases. For example, imaging of the corresponding portions of a device is well-suited to observation of quantities such as layer thickness, thickness uniformity, and interface structure. Surface morphology of a layer in a device structure may also be examined using imaging techniques. For example, pinholes in an oxide layer may be visible by imaging of the surface of the layer.
One of the highest-resolution imaging techniques available is transmission electron microscopy (TEM). A TEM image is created by transmission of high energy (about 60-350 keV) electrons through a very thin sample (a few atomic layers thick). The minimum feature size that can be imaged using a microscopy technique is generally somewhat larger than the wavelength of radiation used, because of diffraction and interference effects. The high electron energies used in TEM correspond to low electron wavelengths, as low as about 0.04 angstroms. The resulting feature sizes resolvable may be as small as one or two angstroms, making TEM a very “high-resolution” technique. There is a price to be paid for this high resolution, however. The thin samples required must be prepared by exacting ion milling techniques which may take several hours.
Scanning electron microscopy (SEM) is another electron-based imaging technique which typically requires minimal sample preparation and can be performed much more rapidly than TEM imaging. An SEM operates by creating a beam of electrons which are accelerated to energies ranging from several hundred to several thousand electron volts. The electron beam is focused to a small diameter and repeatedly scanned across a region of interest of a sample. As the beam strikes the sample's surface, lower-energy secondary electrons are emitted. The yield of secondary electrons depends on many factors, such as the work function of the material, the topography of the sample, and the curvature of the surface. Because different materials may have significantly different work functions, the yield of secondary electrons may be used as a contrast mechanism to distinguish between different materials on a surface. Because changes in topography affect secondary electron yield, one may similarly measure a change in height along the sample's surface. Electron current resulting from the surface-emitted secondary electrons is detected and used to correspondingly control the intensity of pixels on a monitor attached to the SEM. An image of the region being studied is formed by synchronously scanning the electron beam and the screen of the monitor.
The lower-energy electrons used in SEM make it a lower-resolution technique than TEM. Feature sizes on the order of ten angstroms may be resolved by SEM, however, giving the technique a resolution adequate for many aspects of semiconductor device examination. A more significant shortcoming of SEM as compared to TEM may be that interfaces between materials can be more difficult to detect. This is particularly true in the case of interfaces between materials with some similarity in composition, such as silicon/silicide interfaces.
Another difficulty with SEM observations, as well as with other forms of microscopy, is that the area of interest

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