Port interface modules (PIMs) in a multi-port memory...

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C710S010000, C710S012000, C710S306000, C710S314000, C710S315000, C711S149000, C326S038000

Reexamination Certificate

active

07913022

ABSTRACT:
Port Interface Modules (PIMs) are provided for ports of a Multi-Port Memory Controller. The PIMs include logic that is programmable to be compatible with different types of devices, processors or buses that can be connected to the ports. The PIMs can further include protocol bridges to enable one port PIM to connect to a device or another port PIM in a master/slave fashion.

REFERENCES:
patent: 4349870 (1982-09-01), Shaw et al.
patent: 4511964 (1985-04-01), Georg et al.
patent: 4912632 (1990-03-01), Gach et al.
patent: 5651112 (1997-07-01), Matsuno et al.
patent: 5666521 (1997-09-01), Marisetty
patent: 5761478 (1998-06-01), Chen et al.
patent: 5768500 (1998-06-01), Agrawal et al.
patent: 5804986 (1998-09-01), Jones
patent: 5870349 (1999-02-01), Lattimore et al.
patent: 5889987 (1999-03-01), Nelson et al.
patent: 6151682 (2000-11-01), van der Wal et al.
patent: 6329839 (2001-12-01), Pani et al.
patent: 6333935 (2001-12-01), Carr et al.
patent: 6353332 (2002-03-01), Brelet
patent: 6373779 (2002-04-01), Pang et al.
patent: 6567564 (2003-05-01), Van der Wal
patent: 6601130 (2003-07-01), Silvkoff et al.
patent: 6601149 (2003-07-01), Brock et al.
patent: 6662285 (2003-12-01), Douglass et al.
patent: 6754786 (2004-06-01), Suzuki et al.
patent: 6792458 (2004-09-01), Muret et al.
patent: 6799304 (2004-09-01), Hammitt et al.
patent: 6871312 (2005-03-01), Hatley
patent: 6983393 (2006-01-01), Truchard et al.
patent: 7020802 (2006-03-01), Gross et al.
patent: 7072800 (2006-07-01), Fernandez et al.
patent: 7076595 (2006-07-01), Dao et al.
patent: 7120761 (2006-10-01), Matsuzaki et al.
patent: 7146448 (2006-12-01), Davies et al.
patent: 7225301 (2007-05-01), Furtek et al.
patent: 7260688 (2007-08-01), Baxter et al.
patent: 7287196 (2007-10-01), Gerard
patent: 7308540 (2007-12-01), Leijten
patent: 7308564 (2007-12-01), Jenkins, IV
patent: 7454546 (2008-11-01), Lilley
patent: 2003/0036875 (2003-02-01), Peck et al.
patent: 2004/0075690 (2004-04-01), Cirne
patent: 2005/0060456 (2005-03-01), Shrader et al.
patent: 2006/0047992 (2006-03-01), Gerard
STMicroelectronics. Configuring the SPEAr600 multi-port memory controller for external DDR SDRAM. Application Note. Jan. 2010.
ARM Limited. ARM PrimeCell MultiPort Memory Controllerl (PL172). Revision r2p1. Technical Reference Manual. 2002.
Zipcores.com. Multi-ported Memory Controller-Arbiter. Rev. 1.0. 2009.
Microtronix. Avalon Multi-Port SDRAM Controller. User Manual. Version 2.6. Feb. 2010.
Xilinx, Inc. “Gigabit System Reference Design” XAPP536, Jun. 3, 2004, pp. 1-51, v1.1, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
Xilinx, Inc., “High Performance Multi-Port Memory Controller”, XAPP535, Dec. 10, 2004, pp. 1-190, v1.1, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
Lilley, Jennifer R. et al., “Architecture for Dynamically Reprogrammable Arbitration Using Memory”, U.S. Appl. No. 11/341,033, filed Jan. 27, 2006, pp. 1-23, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
Baxter Glenn A. et al. Method and Apparatus for Controlling Access to Memory Circuitry, Serial No. 10/824,967, Filed Apr. 15, 2004, pp. 1-76, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
Baxter, Glenn A. et al., “Method and Apparatus for Controlling Direct Access to Memory Circuitry”, U.S. Appl. No. 10/824,713, filed Apr. 15, 2004, pp. 1-75, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
Borrelli, Christopher, J. et al., “Method and Apparatus for Communicating Data Between a Network Transceiver and Memory Circuitry”, U.S. Appl. No. 10/824,715, filed Apr. 15, 2004, pp. 1-75, available from Xilinx, Inc., 2100 Logic Drive, Jose, CA 95124.
Xilinx, Inc., “Multi Port Memory Controller—MPMC2”, Oct. 20, 2006, 2 pp., v.1.7, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
U.S. Appl. No. 11/707,175, filed Feb. 14, 2007 Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.
U.S. Appl. No. 11/707,108, filed Feb. 14, 2007 Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.
U.S. Appl. No. 11/706,610, filed Feb. 14, 2007 Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Port interface modules (PIMs) in a multi-port memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Port interface modules (PIMs) in a multi-port memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Port interface modules (PIMs) in a multi-port memory... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2713153

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.