Polysilicon/polycide etch process for sub-micron gate stacks

Details Polysilicon/polycide etch process for sub-micron gate stacks Polysilicon/polycide etch process for sub-micron gate stacks

1994-12-20

1996-06-25

Schilling, Richard L.

Etching a substrate: processes

Gas phase etching of substrate

Application of energy to the gaseous etchant or to the...

216 67, 1566431, 156345, 437228, 437238, B44C 122, C03C 1500, C03C 2506

Patent

active

055291970

ABSTRACT:
A method for fabricating a stacked gate array on a semiconductor wafer. The method comprises the steps of providing a reaction chamber having an upper inductive coil and a lower capacitive electrode. The upper inductive coil is adjusted to a relatively low power setting of substantially less than 300 watts. The wafer is placed into the reaction chamber and plasma etched to provide the stacked gate array.

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