Polysilicon line having a metal silicide region enabling...

Details Polysilicon line having a metal silicide region enabling... Polysilicon line having a metal silicide region enabling...

2006-10-17

2006-10-17

Brewster, William M. (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S649000, C438S651000, C438S656000, C438S682000

Reexamination Certificate

active

07122410

ABSTRACT:
By maintaining the gate electrode covered during the process flow for forming metal silicide regions in the drain and source of a field effect transistor, an appropriate metal silicide may be formed on the gate electrode which meets the requirement for aggressive gate length scaling. Preferably, a nickel silicide is formed on the gate electrode, whereas the drain and source regions receive the well-established cobalt disilicide. Additionally, the gate electrode dopant profile is effectively decoupled from the drain and source dopant profile.

REFERENCES:
patent: 5731239 (1998-03-01), Wong et al.
patent: 5953612 (1999-09-01), Lin et al.
patent: 6153485 (2000-11-01), Pey et al.
patent: 6376320 (2002-04-01), Yu
patent: 6458678 (2002-10-01), Spikes, Jr. et al.
patent: 6867130 (2005-03-01), Karlsson et al.
patent: 2004/0084734 (2004-05-01), Matsuo

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