Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2007-01-09
2007-01-09
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C257SE23116, C257SE21502
Reexamination Certificate
active
10963285
ABSTRACT:
A process for packaging semiconductor devices for flip chip and wire bond applications, wherein specific materials of the semiconductor devices are protected during device processing sequences and dicing procedures, has been developed. After definition of copper interconnect structures surrounded by a low k insulator layer, a protective, first photosensitive polymer layer comprised with a low dielectric constant is applied. After definition of openings in the first photosensitive polymer layer exposing portions of the top surface of the copper interconnect structures, a dicing lane opening is defined in materials located between copper interconnect structures. Conductive redistribution shapes are formed on the copper interconnect structures exposed in the openings in the first photosensitive polymer layer, followed by application of a protective, second photosensitive polymer layer. An opening is defined in the second photosensitive polymer layer exposing a portion of the top surface of a redistribution shape followed by placement of a solder ball in this opening. A reflow anneal procedure results in the solder ball wetting and overlying only the portion of the redistribution shape exposed in the opening in the second photosensitive polymer layer. Separation of the solder ball, flip chip regions from the non-solder ball, wire bond regions is accomplished via a dicing procedure performed in the dicing lane.
REFERENCES:
patent: 6187663 (2001-02-01), Yu et al.
patent: 6281115 (2001-08-01), Chang et al.
patent: 2003/0013232 (2003-01-01), Towle et al.
Derwent Abstract Accession No. 2002-664161/71, Korean Patent Abstract only, KR 2002-0030150 A (Hynix Semiconductor Inc) Apr. 24, 2002, “Method for Fabricating Wafer Level Package”.
Kripesh Vaidyanathan
Periasamy Ganesh Vetrivel
Yoon Seung Wook
Ackerman Stephen B.
Agency for Science, Techology and Research
Coleman W. David
Saile Ackerman LLC
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