Polymer de-imprint circuit using negative voltage

Details Polymer de-imprint circuit using negative voltage Polymer de-imprint circuit using negative voltage

2007-05-15

2007-05-15

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S149000, C365S189011

Reexamination Certificate

active

10973580

ABSTRACT:
Briefly, voltages to write a memory cell are adjusted if the memory cell is determined to be imprinted. In one embodiment, a positive voltage not including zero is applied to one of a bit line and a word line and a negative voltage not including zero is applied to another of the bit line and the word line to write a specified logic state to an imprinted memory cell. Neighboring cells do not receive disturb voltages in excess of a disturb voltage threshold.

REFERENCES:
patent: 5835399 (1998-11-01), Jeon
patent: 5953245 (1999-09-01), Nishimura
patent: 6522567 (2003-02-01), Iwanari
patent: 6522570 (2003-02-01), Basceri et al.
patent: 6922350 (2005-07-01), Coulson et al.
patent: 6922351 (2005-07-01), Natori et al.
patent: 2004/0190322 (2004-09-01), Baumann et al.

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