Polyload sram memory cell with low stanby current

Details Polyload sram memory cell with low stanby current Polyload sram memory cell with low stanby current

1997-10-08

1998-12-22

Nelms, David

Static information storage and retrieval

Systems using particular element

Flip-flop

365148, 365161, G11C 1100

Patent

active

058525734

ABSTRACT:
An SRAM cell formed on a semiconductor substrate with low standby current is disclosed. The memory cell includes a first inverter, a second inverter cross-coupled to the first inverter to form a storage element, a first load device coupled to the first inverter, a second load device coupled to the second inverter, a first access transistor coupled to an output port of the first inverter, and a second access transistor coupled to an output port of the second inverter. In this memory cell, the first load device is placed over the second inverter with substantial overlapping therebetween, so that resistance of the first load device increases when an input of the second inverter is at a low potential, thereby decreasing a standby current of the first load device. Similarly, the resistance of the second load device increases when an input of the first inverter is at a low potential.

REFERENCES:
patent: 4841481 (1989-06-01), Ikeda et al.
patent: 5254870 (1993-10-01), Kimura
patent: 5400277 (1995-03-01), Nowak
patent: 5745404 (1998-04-01), Lien et al.

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