Polygonal structure semiconductor device

Details Polygonal structure semiconductor device Polygonal structure semiconductor device

2002-08-09

2004-03-16

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S401000, C257S351000

Reexamination Certificate

active

06707119

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a semiconductor device, specifically to a semiconductor device minimizing a die size, while preventing a weak inversion current.
FIG.
3
and
FIG. 4
are a cross-sectional view and a top view illustrating a prior art device.
A gate electrode
55
is disposed on a first gate insulation film
53
and a second gate insulation film
54
, which is thicker than the first gate insulation film
53
, formed in areas other than areas of a device isolation film
52
on a semiconductor substrate
51
of a first conductivity e.g. P-type, as shown in the figures.
Low impurity concentration N-type source and drain regions (N− layers, drift layers)
56
and
57
are disposed adjacent to the gate electrode
55
through the second gate insulation film
54
.
High impurity concentration N-type source and drain regions (N+ layers)
58
and
59
are disposed between the second gate insulation film
54
and the device isolation film
52
.
Together with a channel region
60
, which is a surface region of the semiconductor substrate
51
between the source and drain regions
56
and
57
under the first gate insulation film
53
, and a channel stopper layer
61
to prevent an inversion, the structure described above makes a so-called LOCOS offset-type semiconductor device.
A conventional transistor is basically shaped like a rectangle. It requires convex regions (shaded regions in
FIG. 4
) protruding from the N− layers
56
and
57
as shown in
FIG. 4
, in order to suppress a weak inversion leakage current.
When disposing a plurality of transistors in a die in the prior art, a width S
2
of a pair of minimum transistors is increased by a width of the convex regions required to suppress the weak inversion leakage current.
SUMMARY OF THE INVENTION
A semiconductor device of this invention is directed to solve the problem addressed above. A gate electrode formed on a substrate of a first conductivity through a gate insulation film, source and drain regions of an opposite conductivity formed adjacent to the gate electrode and a channel region formed between the source and drain regions polygonal in shape. Neighboring transistors are provided such that they are displaced from each other by a predetermined distance.
The gate electrode, the source and drain regions and the channel region can also be hexagonal in shape.
Neighboring transistors are provided such that they are displaced from each other so that convex portions of the gate electrode, the channel and the source and drain regions of a transistor face concave portions of the neighboring transistor. Thereby, a plurality of transistors is laid out efficiently.


REFERENCES:
patent: 4639762 (1987-01-01), Neilson et al.
patent: 4684967 (1987-08-01), Taylor, Sr. et al.
patent: 4833513 (1989-05-01), Sasaki
patent: 5406104 (1995-04-01), Hirota et al.
patent: 5635742 (1997-06-01), Hoshi et al.
patent: 5838050 (1998-11-01), Ker et al.
patent: 5973368 (1999-10-01), Pearce et al.

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