Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Patent
1997-10-30
2000-10-03
Lintz, Paul R.
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
716 11, G06F 1750
Patent
active
061287679
ABSTRACT:
An approach for representing polygons in an integrated circuit (IC) layout is provided. Polygons are represented by one or more wires, which in turn are each represented by one or more wire segments. Each wire segment is represented by a pair of directed line segments. A data structure hierarchy includes polygon data, wire data, wire segment data and branch data. The polygon data represents a set of IC devices to be represented in the IC layout. The wire data represents the wires that represent the polygons and specifies the associated wire segments and associated polygons. The wire segment data represents the wire segments and specifies the associated directed line segments for each wire segment that represent the wires and references the wire data. The branch data specifies connections between wires by specifying the connecting wire segments in the wires. A spacing check between a first polygon and a second polygon involves determining the canonical direction from the first polygon to the second polygon and testing the two closest faces between the polygons. To satisfy a spacing violation, an exclusion zone is constructed around the first polygon and the second polygon is moved a distance outside the exclusion zone which causes the minimum spacing required by a set of predetermined spacing criteria to be satisfied.
REFERENCES:
patent: 5097422 (1992-03-01), Corbin, II et al.
patent: 5113451 (1992-05-01), Chapman et al.
patent: 5416722 (1995-05-01), Edwards
patent: 5515293 (1996-05-01), Edwards
patent: 5581475 (1996-12-01), Majors
patent: 5612893 (1997-03-01), Hao et al.
patent: 5613102 (1997-03-01), Chiang et al.
patent: 5625568 (1997-04-01), Edwards et al.
patent: 5640497 (1997-06-01), Woolbright
patent: 5689433 (1997-11-01), Edwards
W. L. Schiele, Th. Kruger, K.M. Just, F.H. Kirsch, A Gridless Router for Industrial Design Rules, Siemens AG, Semiconductor Group, HL CAD, 27th ACM/IEEE Design Automation Conference, Paper 38.1 1990 no page #.
Xue-Hou, Tan, et al, "Reporting Intersections of C-Oriented Polygons", Transactions of the Institute of Electronics, Information and Communication Engineers, vol. E 73, No. 11, Nov. 1990, pp. 1886-1892, XP-002099144, ISSN 0913-574X, Japan, see p. 1886, col. 1, line 1, p. 1888, col. 1, line 10.
Fokkema, J. T., et al., An Efficient Datastructure and Algorithm for VLSI Artwork Verification, Proceedings IEEE International Conference on Computer Design: VLSI in Computers (ICCD '83), Port Chester, NY, USA, Oct. 31-Nov. 3, 1983, pp. 350-353, XP002099145, ISBN 0-8186-0480-8, 1983, Silver Spring, MD, USA, IEEE Comput. Soc. Pres, USA, see p. 350, col. 1, line 1-p. 350, col. 2, line 6.
Baird, Henry S., "Fast Algorithms for LSI Artwork Analysis" Proceedings of the 14.sup.th Design Automation Conference, New Orleans, LA, USA, Jun. 1977, vol.2, No. 2, pp. 179-209, XP002100128, ISSN 0099-1708, Journal of Design Automation & Fault-Tolerant Computing, May 1978, USA.
Mohan Guruswamy, Robert L. Maziasz, Daniel Dulitz, Srilata Raman, Venkat Chiluvuri, Andrea Fernandez and Larry G. Jones, "CELLERITY: A Fully Automatic Layout Synthesis System for Standard Cell Libraries," 1997, Unified Design System Laboratory, Motorola, Inc. no pg #.
Donald G. Baltus, Thomas Varga, Robert C. Armstrong, John Duh and T.G. Matheson, "Developing A Concurrent Methodology For Standard-Cell Library Generation," 1997, Mentor Graphics Corporation, no pg #.
Martin Lefebvre, David Marple and Carl Sechen, "The Future of Custom Cell Generation in Physical Synthesis," 1997, Design Automation Conference, no pg #.
John Lakos, "Technology Retargeting For IC Layout," 1997, Mentor Graphics Corporation, no pg #.
David Marple, Michiel Smulders and Henk Hegen, "An Efficient Compactor for 45.degree.Layout," Philips Research Laboratories, no date no pg #.
Stephen M. Trimberger, "An Introduction to CAD for VLSI," VLSI Technology, Inc., no date no pg #.
Johannes Waterkamp, Rainer Wicke, Rainer Bruck, Michael Reinhardt and Georg Schrammeck, "Technology Tracking of Non Manhattan VLSI Layout," 1989, 26th ACM/IEEE Design Automation Conference, no pg #.
Bertrand P. Serlet, "Fast, Small, and Static Combinational CMOS Circuits," 1987, Xerox PARC Computer Science Laboratory, 24th ACM/IEEE Design Automation Conference, no pg #.
Chi Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin and Yu-Chin Hsu, "An Efficient Layout Style for Two-Metal CMOS Leaf Cells and Its Automatic Synthesis," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, No. 3, Mar. 1993, no pg #.
Chong-Leong Ong, Joeong-Tyng Li and Chi-Yuan Lo, "GENAC: An Automatic Cell Synthesis Tool," AT&T Bell Laboratories, 1989, 26th ACM/IEEE Design Automation Conference, no pg #.
Charles J. Poirier, "Excellerator: Custom CMOS Leaf Cell Layout Generator," 1989 IEEE, no pg #.
Shmuel Wimer, Ron Y. Pinter and Jack A. Feldman, "Optimal Chaining of CMOS Transistors in a Functional Cell," IEEE Transactions on Computer-Aided Design, vol. CAD-6, No. 5, Sep. 1987, no pg #.
Chao C. Chen and Shau-Lim Chow, "The Layout Synthesizer: An Automatic Netlist-to-Layout System," Cadence Design Systems, Inc., 1989, 26th ACM/IEEE Design Automation Conference, no pg #.
Stan Chow, Hungsen Chang, Jimmy Lam and Youlin Liao, "The Layout Synthesizer: An Automatic Block Generation System," Cadence Design Systems, IEEE 1992 Custom Integrated Circuits Conference, no pg #.
Thomas Revesz, "Clipping Polygons with Sutherland-Hodgman's Algorithm," The C Users Journal--Aug. 1993, no pg #.
Becker Edward A.
Garbowski Leigh Marie
Lintz Paul R.
Palermo Hickman
LandOfFree
Polygon representation in an integrated circuit layout does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Polygon representation in an integrated circuit layout, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Polygon representation in an integrated circuit layout will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-206056