Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-03-17
2003-05-20
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S482000, C438S487000, C438S488000, C438S489000, C257S052000, C257S063000, C257S064000, C257S066000, C349S042000, C349S043000
Reexamination Certificate
active
06566173
ABSTRACT:
CROSS REFERENCE
This application claims the benefit of Korean Patent Application No. 1999-09220, filed on Mar. 18, 1999, under 35 U.S.C. § 119, the entirety of which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the invention
The present invention relates to a thin film transistor (TFT), and more particularly, to a polycrystalline silicon thin film transistor (Poly-Si TFT) and a method of manufacturing the same.
2. Description of Related Art
Conventional polycrystalline silicon thin film transistors (hereinafter referred to simply as “Poly-Si TFTs”) are commonly employed in high-density static random access memory cells (SRAMs) for load pull-up devices, as well as used both as switching elements and as peripheral driver circuitry in large-area active-matrix liquid crystal displays (LCDs).
FIG. 1
is a plan view illustrating a typical Poly-Si TFT of a coplanar type. As shown in
FIG. 1
, a data line BB is arranged in a longitudinal direction and a gate line GB is arranged in a transverse direction perpendicular to the data line BB. A source electrode
18
a
is extended from the data line BB, and a drain electrode
18
b
is spaced apart from the source electrode and contacts with a pixel electrode (not shown). A gate electrode
17
is extended from the gate line GB. A polycrystalline silicon layer
13
is arranged as an active layer between the source and drain electrodes
18
a
and
18
b
nearby the cross point of the data line BB and the gate line GB.
FIG. 2
is a cross-sectional view taken along line II—II′ of FIG.
1
. Referring to
FIG. 2
, the conventional Poly-Si TFT is manufactured as follows. An amorphous silicon (a-Si) is first deposited on a transparent insulating substrate
11
, heat-treated for crystallization through a furnace annealing technique or a laser annealing technique, and then patterned to form a polycrystalline silicon layer
13
. A gate oxidation film
15
, a gate electrode
17
, source and drain electrodes
18
a
and
18
b
, and an interlayer insulating film
19
are sequentially formed using self-align technology.
Electric characteristics of the Poly-Si TFT described above mainly depend on the polycrystalline silicon layer
13
that is an active area. The polycrystalline silicon layer
13
of the Poly-Si TFT formed through the above described method has a higher carrier mobility than amorphous silicon, but also has a substantially higher defect density than the single crystal silicon layer because it includes a large number of grain boundaries randomly arranged and, therefore the grain boundaries prevent carriers from flowing along the channel. As a result, the Poly-Si TFT tends to have a bad electric characteristic such as low carrier mobility.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a Poly-Si TFT having the polycrystalline silicon layer as an active area in which grain boundaries thereof are uniformly arranged to be parallel to the channel direction in which electrons flow.
In order to achieve the above object, the present invention, in a first aspect, provides a polycrystalline silicon thin film transistor connected to a gate line and a data line, including a source electrode contacting the data line; a gate electrode contacting the gate line; a drain electrode spaced apart from the source electrode; a polysilicon layer positioned between and contacting the source and the drain electrodes, and acting as a channel area in which electrons flow; at least one metal layer positioned near the polysilicon layer and parallel to a flow direction of the electrons; and a buffer layer interposed between the metal layer and the polysilicon layer.
The metal layer is entirely overlapped with the polysilicon layer, or is partially overlapped with the polysilicon layer.
The present invention, in another aspect, provides a polycrystalline silicon thin film transistor connected to a gate line and a data line, including a substrate; at least one metal layer parallel to the gate line on the substrate; a first insulating layer covering the at least one metal layer and the exposed substrate; a polysilicon layer on the first insulating layer; a source electrode contacting the polysilicon layer and the data line; a drain electrode spaced apart from the source electrode and contacting the polysilicon layer; a second insulating layer on the polysilicon layer; and a gate electrode on the second insulating layer and connected to the gate line.
The present invention, in another aspect, further provides a method of forming a polysilicon layer which is used as a channel of a thin film transistor, including the steps of: forming at least one metal layer parallel to the channel direction; forming an insulating layer covering the metal layer; forming an amorphous silicon layer on the insulating layer; and heat treating the amorphous silicon layer, thereby converting the amorphous silicon layer into a polysilicon layer.
The heat treating process is done by a laser annealing technique.
The foregoing and other objectives of the present invention will become more apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
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Lee Jr. Granvill D
LG Philips LCD Co., Ltd.
Smith Matthew
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