Semiconductor device manufacturing: process – Making device or circuit responsive to nonelectrical signal – Physical stress responsive
Reexamination Certificate
2000-01-14
2001-04-03
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Making device or circuit responsive to nonelectrical signal
Physical stress responsive
C438S052000, C438S933000
Reexamination Certificate
active
06210988
ABSTRACT:
BACKGROUND
This invention relates to micro-electromechanical systems (MEMS), and more particularly to the fabrication of microstructures using structural and sacrificial films.
Surface micromachining is the fabrication of thin-film microstructures by the selective removal of a sacrificial film. Since the 1980s, polycrystalline silicon (poly-Si), deposited by low-pressure chemical vapor deposition (LPCVD), has become established as an important microstructural material for a variety of applications. Silicon dioxide (SiO
2
) is typically used for the sacrificial layer and hydrofluoric acid (HF) is used as the selective “release” etchant in poly-Si micromachining. The successful application of poly-Si to inertial sensors, for example, is owing to the excellent mechanical properties of poly-Si films and to the widespread availability of deposition equipment for poly-Si and SiO
2
films, both of which are standard materials for integrated-circuit fabrication.
Co-fabrication of surface microstructures and microelectronic circuits in a modular fashion is advantageous in many cases, from the perspectives of system performance and cost. Given the maturity of the microelectronics industry and the complexity and refinement of integrated-circuit processes, it is highly desirable if the MEMS can be fabricated after completion of the electronic circuits with conventional mettallization, such as aluminum (Al) metallization. While this “MEMS-last” strategy is infeasible for poly-Si microstructures because the deposition and stress-annealing temperatures for poly-Si films are much too high for aluminum or copper interconnects to survive, the MEMS-last strategy is nonetheless very desirable.
The state-of-the-art poly-Si integration strategy is to fabricate the thin-film stack of structural and sacrificial films prior to starting the electronic circuit process. There are several practical disadvantages to this “MEMS-first” approach. First, the highly tuned and complex electronics process may be adversely affected by the previous MEMS deposition, patterning, and annealing steps. For this reason, commercial electronics foundries are unlikely to accept the pre-processed wafers as a starting material. Second, the planarity of the wafer surface must be restored after completion of the MEMS thin-film stack, which can be accomplished by fabricating the MEMS in a micromachined well or by growing additional silicon through selective epitaxy. Third, the release of the structure occurs at the end of the electronics process and the electronic circuits must be protected against the hydrofluoric acid etchant. Finally, the MEMS-first approach requires that the MEMS and electronics be located adjacent to each other, with electrical interconnections that contribute significant parasitic resistance and capacitance and thereby degrade device performance.
SUMMARY
In one aspect, the invention features a process for forming a micro-electromechanical system on a substrate. The process includes depositing a sacrificial layer of silicon-germanium onto the substrate; depositing a structural layer of silicon-germanium onto the sacrificial layer, where the germanium content of the sacrificial layer is greater than the germanium content of the structural layer; and removing at least a portion of the sacrificial layer.
In another aspect, the invention is directed to a process for forming a micro-electromechanical system. The process includes depositing onto a substrate a sacrificial layer of silicon oxide; depositing onto the sacrificial layer a structural layer of Si
1-x
G
x
, where 0<x≦1, at a temperature of about 650° C. or less; and removing at least a portion of the sacrificial layer.
In yet another aspect, the invention is directed to a process which for forming a micro-electromechanical system, comprising the steps of depositing onto a substrate a sacrificial layer of polycrystalline germanium; depositing onto the sacrificial layer a structural layer of Si
1-x
Ge
x
, where 0<x≦1 at a temperature of about 650° C. or less; and removing at least a portion of the sacrificial layer.
In another aspect, the invention is directed to a process which includes depositing a ground plane layer of Si
1-x
Ge
x
, where 0.6<x<0.8; depositing onto the ground plane layer a sacrificial layer; depositing onto the sacrificial layer a structural layer of Si
1-x
Ge
x
, where 0<x≦1, at a temperature of about 650° C. or less; and removing at least a portion of the sacrificial layer.
Various implementations of the invention may include one or more of the following features. The process may form one or more transistors on the substrate where the transistors are formed before the sacrificial and structural layers are deposited onto the substrate. The transistors may be formed using Cu metallization or Al metallization. The transistors may be formed without metallization before the sacrificial and structural layers are deposited onto the substrate and are metalized after the sacrificial and structural layers are deposited. The transistors may be MOS transistors or bipolar transistors.
The sacrificial layer may be composed of Si
1-x
G
x
, where 0.4≦x≦1. The sacrificial layer and the structural layer may be deposited at a temperature of about 550° C. or less. The germanium concentration of the structural layer may vary through its depth. The process may remove portions of the structural layer to achieve a desired three-dimensional shape. The sacrificial layer may be completely removed. The sacrificial layer may be removed by exposing it to a solution comprising hydrogen peroxide, ammonium hydroxide, and water, or HF. Before the sacrificial layer is exposed to HF, amorphous silicon may be deposited on the substrate.
In another aspect, the invention is directed to a micro-electromechanical system. The system includes a substrate; one or more structural layers of Si
1-x
Ge
x
, formed on the substrate, where 0<x≦1; and one or more transistors formed on the substrate.
Various implementations of the microelectromechanical system may include one or more of the following features. The micro-electromechanical system may feature a glass or a silicon substrate. It may comprise at least portions of one or more sacrificial layers of silicon-germanium formed under structural layers, where the germanium content of the one or more sacrificial layers is greater than the germanium content of the respective structural layers. The system may also comprise at least portions of one or more sacrificial layers of silicon oxide formed under structural layers. The one or more transistors in the micro-electromechanical system may be MOS transistors or bipolar transistors.
The one or more structural layers in the micro-electromechanical system are deposited above the one or more transistors. The one or more structural layers may be deposited onto an upper level of a metal interconnect of the one or more transistors. The one or more structural layers include a ground plane which is electrically connected to the upper level of the metal interconnect. The one or more structural layers may form a resonator, or may be incorporated into an optical device.
The details of one or more implementations of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.
A principal advantage of using poly-silicon-germanium is its much lower deposition temperature than LPCVD poly-Si; furthermore, a dopant-activation and residual stress annealing step, if even necessary, can be conducted at a much lower temperature than for LPCVD poly-Si. In fact, the in situ doped, p-type poly-silicon-germanium (poly-Si
(1-x)
Ge
x
) does not require an annealing step, because its as-deposited resistivity, residual stress and stress gradient are sufficiently low for many MEMS applications. In situ doped p-type poly-Si
(1-x)
Ge
x
films may be used as the structural layer, both to maximize the deposition rate and to minimize
Franke Andrea
Howe Roger T.
King Tsu-Jae
Chaudhuri Olik
Coleman William David
Egan, III William J.
The Regents of the University of California
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