Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Polycrystalline semiconductor
Reexamination Certificate
2006-11-14
2006-11-14
Sarkar, Asok Kumar (Department: 2891)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Polycrystalline semiconductor
C257SE21572
Reexamination Certificate
active
07135391
ABSTRACT:
A structure and method of fabrication for MOSFET devices with a polycrystalline SiGe junction is disclosed. Ge is selectively grown on Si while Si is selectively grown on Ge. Alternating depositions of Ge and Si layers yield the SiGe junction. The deposited layers are doped, and subsequently the dopants outdiffused into the device body. A thin porous oxide layer between the polycrystalline Ge and Si layers enhances the isotropy of the SiGe junctions.
REFERENCES:
patent: 5246886 (1993-09-01), Sakai et al.
patent: 5250452 (1993-10-01), Ozturk et al.
patent: 5571744 (1996-11-01), Demirlioglu
patent: 5646073 (1997-07-01), Grider
patent: 5818100 (1998-10-01), Grider
patent: 6352942 (2002-03-01), Luan et al.
patent: 2005/0079691 (2005-04-01), Kim et al.
Ajmera Atul
Chan Kevin Kok
Jones Erin C.
Miller Rober J.
Sai-Halasz George
Sarkar Asok Kumar
Trepp Robert M.
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