Polycide gate MOSFET for integrated circuits

Details Polycide gate MOSFET for integrated circuits Polycide gate MOSFET for integrated circuits

1992-01-27

1993-05-25

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257408, 257755, 257757, 257764, H01L 2976, H01L 2348

Patent

active

052143058

ABSTRACT:
A method is described for fabricating a lightly doped drain MOSFET integrated circuit device which overcomes the peeling problems of refractory metal silicide layers on a polycide gate. The process of this invention has been simplified by not using several of the high thermal cycle process steps believed to be necessary for successfully making a polycide gate lightly doped drain MOS FET integrated circuit. These steps are (1) the thermal oxidation after the polycide etching step, (2) the densification step after the blanket deposition of silicon dioxide layer for the spacer preparation, and (3) the silicon oxide capping of the refractory metal silicide layer after the spacer formation by anisotropically etching. The result is a process that provides a non-peeling polycide gate lightly doped drain MOS FET integrated circuit device.

REFERENCES:
patent: 4690730 (1987-09-01), Tang et al.
patent: 4876213 (1989-10-01), Pfiester
patent: 5073514 (1991-12-01), Ito et al.
patent: 5089432 (1992-02-01), Yoo
patent: 5097300 (1992-03-01), Takeuchi

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