Poly tip and self aligned source for split-gate flash cell

Details Poly tip and self aligned source for split-gate flash cell Poly tip and self aligned source for split-gate flash cell

1998-05-27

2001-07-10

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S321000, C257S322000, C257S324000

Reexamination Certificate

active

06259131

ABSTRACT:

BACKGROUND OF THE INVENTION
(1). Field of the Invention
The present invention relates to split-gate memory cells used in flash EEPROMs (Electrically Erasable Programmable Read Only Memories), and in particular, to a method of forming a novel poly tip and a self-aligned source in a split-gate flash cell.
(2). Description of the Related Art
Programming and erasing of an EEPROM cell is accomplished electrically by using Fowler-Nordheim (F-N) tunneling as is well known in prior art. F-N tunneling, in turn, is enhanced usually by providing, what is known as a gate bird's beak (GBB) at the corner of a gate structure of the memory cell. However, the forming of a GBB must be optimized carefully, for, otherwise, the GBB can encroach under the gate edge and degrade the programmability of submicron memory cells. That is, the dimensions and shape of the GBB, which is described below more in detail in relation to nonvolatile memories, play an important role in transferring current to and fro between the substrate and the floating gate, and hence the charging speed of the memory cell, and the amount of surface current leakage that takes place around and near the bird's beak. It is disclosed later in the embodiments of the present invention a novel approach to form a polysilicon gate tip (poly tip) in place of gate bird's beak for enhanced F-N tunneling.
Among the nonvolatile read only memories, such as masked-ROMs, Electrically Programmable (EP-ROMs), EEPROMs have been known as one type of nonvolatile memory semiconductor devices capable of electrically writing and erasing information. However, EEPROMs require two transistors to operate. In Flash EEPROM, the memory cell includes one transistor, and the contents of all the memory's cells can be erased simultaneously through the use of an electrical erase signal. Hence, with Flash memory, in addition to gaining speed in having the cells erased much more rapidly, higher levels of integration can be achieved with fewer devices.
The unit cell of an EEPROM memory device is usually comprised of a silicon substrate provided with a source and a drain, and two polysilicon gates; that is, a MOS transistor having a channel defined by the source and drain regions, a floating gate to which there is no direct electrical connection and a control gate with a direct electrical connection. The floating gate is separated from the substrate by an insulating layer of, for example, silicon oxide. The control gate is generally positioned over the floating gate with a layer of insulating material separating the two gates. To program a transistor, electron is injected from the substrate through the insulator and is stored on the floating gate of the transistor. The amount of charge is set to one of two levels to indicate whether the cell has been programmed “on” or “off.” “Reading” of the cell's state is accomplished by applying appropriate voltages to the cell source and drain, and to the control gate, and then sensing the amount of charge on the floating gate. To erase the contents of a cell, the programming process is reversed, namely, electrons are removed from the floating gate by transferring them to the control gate through the insulator. A fairly recent technology is “flash” memories in which the entire array of memory cells, or a significant subset thereof, is erased simultaneously. Flash EEPROMs combine the advantages of UV-erasable EPROMS and floating-gate EEPROMs. They offer high density, small cell size, the well-known hot-electron writeability of EPROMs, together with the easy reusability, on-board reprogrammability, and electron-tunneling erasure feature of EEPROMs (See S. Wolf, “Silicon Processing for the VLSI Era,” vol. 2, Lattice Press, Sunset Beach, Cali., 1990, pp. 632-634.)
As stated earlier, programming and erasing of an EEPROM is accomplished electrically and in-circuit by using Fowler-Nordheim tunneling. Basically, a sufficiently high voltage is applied to the control gate and drain while the source is grounded to create a flow of electrons in the channel region in the substrate. Some of these electrons gain enough energy to transfer from the substrate to the floating gate through the thin oxide layer by means of Fowler-Nordheim tunneling. The tunneling is achieved by raising the voltage level on the control gate to a sufficiently high value of about 12 volts. As the electronic charge builds up on the floating gate, the electric field is reduced, which reduces the electron flow. When, finally, the high voltage is removed, the floating gate remains charged to a value larger than the threshold voltage of a logic high that would turn it on. Thus, even when a logic high is applied to the control gate, the EEPROM remains off. Since tunneling process is reversible, the floating gate can be erased by grounding the control gate and raising the drain voltage, thereby causing the stored charge on the floating gate to flow back to the substrate. Of critical importance in the tunneling region is the quality and the thinness of the tunneling oxide separating the floating gate from the substrate. Usually a thickness of between about 80 to 120 Angstroms is required to facilitate Fowler-Nordheim tunneling.
A cross section of a conventional Flash EEPROM is shown in FIG.
1
. Drain impurity diffusion layer (
16
) and a source impurity diffusion layer (
17
) are formed on a main surface of the semiconductor substrate (
10
) and are spaced from each other by a predetermined distance with a channel region therebetween. The conventional Flash EEPROM further includes a floating gate electrode (
13
) formed on the channel region with a first gate oxide film (
12
) therebetween, a control gate electrode (
15
) formed on the floating gate electrode (
13
) with an insulating film (
14
) therebetween, an interlayer thermal oxide film (
18
) covering the semiconductor substrate (
10
), floating gate electrode (
13
) and control gate electrode (
15
), and an interlayer insulating film (
19
) covering the interlayer thermal oxide film (
18
). Gate bird's beak oxide films (
20
) are formed at opposite ends of the first gate oxide film (
12
) and opposite end of the insulating film (
14
). The interlayer insulating film (
19
) contains impurity such as boron or phosphorous. The purpose of the interlayer thermal oxide film (
18
) is to prevent the movement of impurity such as boron of phosphorous of the interlayer insulating film (
19
) into the semiconductor substrate (
10
), control gate electrode (
15
) or floating gate electrode (
13
) and thus to prevent change of the electrical characteristics thereof.
After the final step of forming the interlayer insulating film (
19
) to cover the interlayer thermal oxide film (
18
) shown in
FIG. 1
, usually heat treatment by a reflow method is carried out to flatten the interlayer insulating film (
19
). During this process as well as during thermally growing the thermal oxide layer (
18
) by means of wet oxidation, oxidizer (H
2
O) penetrates the interlayer insulating film (
19
) and interlayer thermal oxide film (
18
). This causes further oxidization between the semiconductor substrate (
10
) and the ends of the floating gate electrode (
13
), and between the control gate electrode (
15
) and the floating gate electrode (
13
). As a result, the gate bird's beak oxide films (
20
) are formed. Consequently, the lower end of the floating gate electrode (
13
) contacts the gate bird's beak oxide films (
20
) so that the lower end of the floating gate electrode (
13
) is oxidized to a large extent as compared with the other portions.
The gate bird's beak oxide film (
20
) can form either at the lower end of the floating gate (
13
) and the source impurity diffusion layer (
17
), or at the lower end of the floating gate near the drain impurity diffusion layer (
16
), or at both locations. In these cases, the conventional “beak” of the bird's beak is usually long and elongated, thus increasing the size of the cell and at the same time providing paths for current leakage and, therefore

Affiliated with

Also associated with

Rating

Poly tip and self aligned source for split-gate flash cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Poly tip and self aligned source for split-gate flash cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Poly tip and self aligned source for split-gate flash cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2540895