Poly LDD self-aligned channel transistors

Details Poly LDD self-aligned channel transistors Poly LDD self-aligned channel transistors

1995-05-24

1996-09-24

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257344, 257408, 257333, 257396, 257377, 257900, H01L 27108

Patent

active

055593577

ABSTRACT:
Short channel MOS devices are provided with two distinct doped polysilicon contacts: (a) doped polysilicon layers in contact with the source or drain regions (the LDD regions) and extending underneath the oxide region to abut the oxide liner of the trench sidewalls; and (b) polysilicon source and drain contacts in contact with the doped polysilicon layers. The shallow channel doping region is self-aligned with the lightly doped source and drain regions; this ensures vertically engineered profiles that give high punchthrough voltages and an excellent short channel control. The use of the doped polysilicon layers ensures self-alignment of source/drain diffusions and channel and prevents etching of TEOS in the trenches, which prevents exposure of trench sidewalls and formation of parasitic devices in the sidewalls. Further, use of doped polysilicon layers to form the LDD regions by diffusion results in high currents and shallow junctions. The devices also include an insulation spacer that separates the gate electrode from the oxide region between the source and drain contacts and the gate electrode, the insulation spacer preferably made of a nitride. To relieve stress, a thin oxide layer is provided between the insulation spacer and the oxide region. The insulation spacers increase drive currents and move the peak electric field under the spacers, thereby improving device reliability. The insulation spacers also make it possible to define effective channel lengths, thereby avoiding the use of advanced lithography.

REFERENCES:
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patent: 4697198 (1987-09-01), Komori et al.
patent: 4974055 (1990-11-01), Haskell
patent: 4977108 (1990-12-01), Haskell
patent: 5045901 (1991-09-01), Komori et al.
A. F. Tasch et al, "Limitations of LDD Types of Structures in Deep-Submicrometer MOS Technology", IEEE Electron Device Letters, Vo. 11, No. 11, pp. 517-519 (Nov. 1990).
R. Izawa et al, "Impact of the Gate-Drain Overlapped Device (GOLD) for Deep Submicrometer VLSI", IEEE Transactions on Electron Devices, vol. 35, No. 12, pp. 2088-2093 (Dec. 1988).
D. S. Wen et al, "A Fully Planarized 0.25 .mu.m CMOS Technology", Digest of 1991 Symposium on VLSI Technology, pp. 83-84.
K. Hieda et al, "Sub-Half Micrometer Concave MOSFET with Double LDD Structure", IEEE Transactions on Electron Devices, vol. 39, No. 3, pp. 671-676 (Mar. 1992).

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