Poly fuse trim cell

Details Poly fuse trim cell Poly fuse trim cell

2002-06-25

2003-11-25

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having fuse element

C365S042000

Reexamination Certificate

active

06654304

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of trimming circuits, and particularly to poly fuse trim cells.
2. Description of the Related Art
Poly fuse trim cells are used in many applications in which it is necessary to permanently program the digital values of one or more bits. For example, an 8-bit digital-to-analog converter (DAC) might be employed to provide a correction voltage to a particular circuit. Eight poly fuse trim cells could be programmed to provide the eight digital input bits to the DAC which cause it to produce the desired correction voltage.
A typical poly fuse trim cell is shown in
FIG. 1. A
poly fuse F
1
is connected in series with a transistor MN
0
at a node
10
, with F
1
and MN
0
connected between supply rails VDD and GND. In response to a TRIM control signal (preferably buffered with one or more inverters U
1
, U
2
), MN
0
conducts a current sufficient to cause F
1
to “blow” and become an open-circuit. A current source circuit
12
is connected to node
10
; circuit
12
is made of a transistor MN
1
, which provides a small current I
1
(such as 2-5 uA) in response of a bias voltage VB. An inverter U
3
inverts the logic level at node
10
and presents it at its output, which serves as the output OUT of the trim cell.
In operation, when the fuse is intact, the current through F
1
(I
1
) causes a very small voltage drop across F
1
, and makes node
10
about equal to VDD (“high”), with the output of inverter U
3
producing a logic “low” at OUT. When the fuse has been blown open by asserting the TRIM signal, the current I
1
pulls node
10
down to near GND (“low”), making OUT a logic “high”. In this way, the state of OUT is “programmed” by either blowing F
1
open or leaving it intact.
One drawback of this approach is that, for cells having fuses that are to remain intact (i.e., cells programmed to permanently produce a “low”), the pull-down current I
1
—while insufficient to affect the logic level of node
10
—still exists as a quiescent current I
Q
(=I
1
) that flows through F
1
and MN
1
. This can pose a problem when a number of such trim cells are used in a low power application. For example, if 20 poly fuse trim cells are used on a particular integrated circuit, the current consumption just for these cells can be 40-100 &mgr;A, which may be unacceptably high.
SUMMARY OF THE INVENTION
A poly fuse trim cell is presented which overcomes the problems noted above, reducing or eliminating the quiescent current of cells having intact poly fuses.
The present poly fuse trim cell includes a poly fuse and a transistor connected together at a first node; as before, the transistor conducts a current necessary to blow open the fuse in response to a control signal. The cell also includes a current source circuit, a switching transistor, and a two-input logic gate; the switching transistor's current circuit is connected between the first node and the current source circuit. The logic gate is connected to the first node at one input, and to a reset signal at its second input. The output of the logic gate provides the output of the cell, and is also connected to control the switching transistor.
The current source circuit, logic gate and switching transistor form a latch. In operation, when the fuse is intact, the logic gate output is in a logic “low” state such that the switching transistor is off (assuming an N-type transistor). This prevents current flow through the current source circuit, thereby making the cell's quiescent current zero when it's fuse is intact. When the fuse is blown open, the logic gate output goes “high” upon the occurrence of a reset signal, which turns on the switching transistor and allows the current source circuit to pull down the first node. In this way, the current consumption of a cell or a plurality of cells is reduced when compared with the prior art cell, assuming that the poly fuses of at least some of the trim cells remain intact.


REFERENCES:
patent: 5047664 (1991-09-01), Moyal
patent: 5384727 (1995-01-01), Moyal et al.
patent: 5412594 (1995-05-01), Moyal et al.
patent: 6157241 (2000-12-01), Hellums
Precision CMOS Single Supply Rail-to-Rail Input/Output Wideband Operational Amplifiers, Analog Devices, Inc., AD8601/AD8602/AD8604, pp. 1-16, (2000).
Preliminary Technical Data, Precision Low Noise CMOS Rail-to-Rail Input/Output Operational Amplifiers, Analog Devices, Inc., AD8605/AD8606/8608, pp. 1-4, (1997).

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