Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-10-25
2004-03-30
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S344000, C257S064000, C257S065000, C257S072000, C257S075000, C349S106000, C349S138000, C349S056000, C349S059000, C349S043000, C438S149000, C438S151000, C438S154000
Reexamination Certificate
active
06713825
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to poly-crystalline thin film transistors and to their fabrication. More particularly, the present invention relates to poly-crystalline thin film transistors having multiple section gate electrodes and multiple section semiconductor layers.
2. Description of the Background Art
Thin film transistors used in active matrix liquid crystal displays are typically made of amorphous silicon (a-Si). Amorphous silicon is advantageous in that it enables large area displays that can be fabricated at low temperature on low-cost glass substrates. However, since the mobility of a-Si thin film transistors is low, such transistors are not well suited for LCD drive applications. In contrast, poly-crystalline silicon thin film transistors have high mobility. This makes them interesting candidates for both LCD array and driving circuits.
FIG. 1
illustrates a poly-crystalline (p-Si) silicon transistor that is suitable for driving a pixel of a liquid crystal display. The transistor in
FIG. 1
is a poly-crystalline silicon, CMOS (Complimentary Metal Oxide Semiconductor) thin film transistor that includes a buffer layer
3
on a transparent glass substrate
1
. On the buffer layer
3
is a semiconductor layer having a p-Si intrinsic channel layer
4
, an LDD region
5
that is doped with an impurity at a low concentration, and source and drain regions
6
that are impurity doped at a high concentration. A gate insulation layer
9
is formed over the substrate
1
, and a gate electrode
2
is on the gate insulation layer
9
and over the channel layer
4
. An interlayer
13
is deposited over the gate electrode
2
and over the gate insulation layer
9
. The interlayer
13
includes via holes that expose the source and drain regions
6
. Source and drain electrodes
11
are then formed on the interlayer
13
and in the via holes so as to contact the source and drain regions
6
. A passivation layer
15
is then deposited over the interlayer
13
and source and drain electrodes
11
, and a drain contact hole is formed through the passivation layer
15
. A pixel electrode
17
is then formed on the passivation layer
15
and in the drain contact hole so as to contact the drain electrode
11
.
As mentioned above, poly-crystalline silicon has a high mobility. Thus, the switching time of the transistor shown in
FIG. 1
is fast, which reduces signal delays. In addition, p-Si driving circuits that use such CMOS thin film transistors can be formed along with pixel driving thin film transistors on the same liquid crystal panel substrate. This simplifies the fabrication processes.
However, poly-crystalline silicon thin film transistors constructed as shown in
FIG. 1
tend to have higher leakage currents than amorphous silicon thin film transistor switching devices. High leakage causes the voltage applied to a pixel to drift, which can result in flicker and poor picture quality in a liquid crystal display.
As is well known, leakage current in a poly-crystalline silicon thin film transistor is related to the electric field distribution between the drain and source regions and the gate. While the poly-crystalline silicon thin film transistor illustrated in
FIG. 1
reduces leakage current by incorporating the LDD region
5
, which reduces the electric field along the sides of the source and drain regions, such poly-crystalline silicon thin film transistors have relatively high parasitic resistances and a relatively low ON-state current.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a low current leakage poly-crystalline thin film transistor that has a high ON-state current.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, there is provided a poly-crystalline thin film transistor having a buffer layer on a substrate, and a poly-crystalline semiconductor layer on the buffer layer. The poly-crystalline semiconductor layer includes a channel layer, offset regions along both sides of the channel layer, and sequential doping regions along sides of the offset regions. The doping concentration of the sequential doping regions sequentially changes. Source and drain regions are formed along sides of the sequential doping regions. A gate insulation layer is on the semiconductor layer. A gate electrode is on the gate insulation layer. The gate electrode includes both a main gate electrode and auxiliary gate electrodes. An interlayer covers the gate electrode. Source and drain electrodes on the interlayer pass through the interlayer to connect to the source and drain regions. Beneficially, the substrate is glass.
To achieve the above objects, there is also provided a poly-crystalline thin film transistor fabrication method that includes forming a poly-crystalline semiconductor layer on a buffer layer on a substrate. A gate insulation layer having downwardly tapered sections over locations where sequentially doped regions are to be is formed over the poly-crystalline semiconductor layer. A metal layer is formed on the gate insulation layer. That metal layer is then patterned to form a gate electrode comprised of a main gate electrode and auxiliary gate electrodes. The semiconductor layer is then impurity doped while using the gate electrode as masks so as to form a channel layer, offset regions, sequential doping regions, and source and drain regions. An interlayer is then deposited and contact holes that expose portions of the source and drain electrodes are formed through the interlayer. Source and drain electrodes are then formed on the interlay such that the source and drain electrodes respectively contact the source and drain regions. Additionally, a passivation layer can be formed over the source and drain electrodes.
REFERENCES:
patent: 5648277 (1997-07-01), Zhang et al.
patent: 5835172 (1998-11-01), Yeo et al.
patent: 5898188 (1999-04-01), Koyama et al.
patent: 5953598 (1999-09-01), Hata et al.
patent: 6569717 (2003-05-01), Murade
Flynn Nathan J.
Forde Remmon R.
LG. Philips LCD Co. Ltd.
McKenna Long & Aldridge LLP
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